Hi Champs,
We are looking for SPRS866G Table8-7.
According to this table, when C66x Core0 transfer EDMA between DDR3A and L1/L2 cache, this MPAX setting is assigned to PrivID=0.
Is this correct ?
Regards,
Kz777
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.