TMS320C6748: TMS320C6748

Ashrumochan NathSharma

Intellectual 400 points

Part Number: TMS320C6748
Other Parts Discussed in Thread: TMDSLCDK6748, OMAP-L138, OMAPL138

Dear Friends,

I have TMS320C6748 Dev kit.

I want to do external Memory interface using EMIF to the FLASH Memory and DDR2 available on Dev board.

Can Anybody tell me or suggest me how to do ,any reference code and document is really needed?

Flash available on board:-MT29F4G16ABADAH4

DDR2 available on board:-SDRAM 128 MB K4T1G164QFBCE7

Regards,

Ashrumochan

over 6 years ago

0 Yordan Kovachev over 6 years ago

TI__Guru**** 161600 points

Are you using TMDSLCDK6748? or is this a custom board?

Best Regards,
Yordan

0 Ashrumochan NathSharma over 6 years ago in reply to Yordan Kovachev

Intellectual 400 points

Hi Yordan Kovachev,

Thanks for asking. I am having LCDK Kit of TMS320C6748 Rev A7A.

Regards,

Ashrumochan

0 Yordan Kovachev over 6 years ago in reply to Ashrumochan NathSharma

TI__Guru**** 161600 points

Ok, in that case the EMIFA is connected to the NAND flash, meaning you can't use EMIFA to access DDR2.

Unfortunately there aren't any reference example projects for EMIFA (Nand).
You can take a look at the serial boot utilities:
processors.wiki.ti.com/.../Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138

e2e.ti.com/.../636036

Best Regards,
Yordan

0 Ashrumochan NathSharma over 6 years ago in reply to Yordan Kovachev

Intellectual 400 points

Hi yordan,

Thanks for your feedback .I am able to do NAND Flash with EMIFA with CS[3] .

As i go through the EMIF module through CS[ ] bit we can access the DDR2 also.

Can you just clarify me that?

Regards,

Ashru

0 Yordan Kovachev over 6 years ago in reply to Ashrumochan NathSharma

TI__Guru**** 161600 points

Hi,

Take a look at the LCDK schematic, page 8:

DDR is connected to CPU_DDR_CSn (DDR_CSn on OMAP_L138 side). This is still an emif (or ddr controller), but this is NOT the EMIFA interface. You won't be able to access it on any EMIFA_CSn address spaces.

See Section 6.10.1 EMIFA Asynchronous Memory Support & Section 6.10.2 EMIFA Synchronous DRAM Memory Support from OMAP_L138 Datasheet.

EMIFA -> Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2])

The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1. It
has a single SDRAM chip select (EMA_CS[0]).

Best Regards,
Yordan

0 Ashrumochan NathSharma over 6 years ago in reply to Yordan Kovachev

Intellectual 400 points

Thanks Yordan for clarifying me.

As per the schematic in LCDK Rev A7A ., the DDR2 is as Parallel Interfaced.

So Can you provide me any reference code for this as in starter ware no reference is available for DDR2?

Regards,

Ashrumochan

0 Yordan Kovachev over 6 years ago in reply to Ashrumochan NathSharma

TI__Guru**** 161600 points

Hi,

You can refer to the GEL files (see the memory tests) in ~/ti/ccsv8/ccs_base/emulation/boards/lcdkomapl138/gel/OMAP-L138_LCDK.gel.

Or the board diagnostics: /ti/pdk_omapl138_1_0_7/packages/ti/board/diag/mem/src/mem_test.c.

Best Regards,
Yordan

0 Yordan Kovachev over 6 years ago in reply to Yordan Kovachev

TI__Guru**** 161600 points

Note that I am referring to the latest Processor SDK RTOS.

Best Regards,
Yordan

0 Ashrumochan NathSharma over 6 years ago in reply to Yordan Kovachev

Intellectual 400 points

Thanks Yordan,

I will look after this.

Regrads,

Ashru

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TMS320C6748: TMS320C6748