AM5748: The arbitration of MPU-EMIF direct access and DMA transfer on AM5748

Nomo

Part Number: AM5748

Hello,

We have some questions about the relationship between DMA transfer and MPU-EMIF direct access on AM5748.
There are two DMA module, System DMA and Enhanced DMA, so could you confirm the following questions against each DMA?

1.While DMA is transferring data to DRAM, is A15 able to access DRAM directly (MPU -> EMIF -> SDRAM)?
In other words, is A15 able to interrupt the other module's transaction of DMA access?

2.In above case, is DMA able to suspend the processing transaction and release the bus (channel) resource?

3.If the answer of question 2 is yes, could you tell us the timing when the bus resource is released?
We want to know, for example, the timing is the end of block transfer, the end of burst transfer, or something.

Best Regards,
Nomo

over 6 years ago

0 JJD over 6 years ago

TI__Guru* 86550 points

Nomo,
1. It depends on what arbitration scheme and priority you have setup for the DMA and A15 masters. The behavior will differ if the A15 has a lower or higher priority relative to DMA
2. Yes, but again, it will depend how it is setup. A lot of this is described in Chapter 16 of the TRM, where Thread Budget Allocation is discussed.
3. There are two FIFOs you can setup, one for high priority channels and one for low priority channels. Section 16.1.4.11 describes how to setup the FIFO budget for each channel. This will determine how much of the FIFO is resevered for Hi/low priority channels. The port access scheduler will arbitrate both read and write priorities and queues to send/receive data on the DRAM bus. More info can be found in the Logical Transfer Overview section 16.1.4.3 of the TRM.

Regards,
James

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AM5748: The arbitration of MPU-EMIF direct access and DMA transfer on AM5748