Linux/PROCESSOR-SDK-AM437X: AM437x LPDDR Timing issue

Hi,

Please post the EMIF tool spreadsheet.

I attached emif tool and elpida datasheet.

I think it is related with ead latency in "EMIF4D_DDR_PHY_CTRL_1". But when I tried it various combination, it failed.

thanks.

SPRAC70_AM437x_EMIF_Configuration_Tool_V20 lpddr_V2 (1).xlsx

E1775E40 (1).pdf

Please also use CCS and JTAG to run this script file:

https://git.ti.com/sitara-dss-files/am43xx-dss-files/blobs/raw/master/am43xx-ddr-analysis.dss

Directions on how to run the file can be found here:

https://git.ti.com/sitara-dss-files/am43xx-dss-files/blobs/master/README

The script should be run after the EMIF has been configured.  It will output 2 files to your desktop, a txt file and a csv file.  Please zip them up and attach them.

I attached zip file it has two files. One is analysis.txt and the other is raw regdump csv file.

There is no jtag on the current board. I use uart to get the results, so the indentation may not be the same as the original tool.

Thanks

lpddr2_analysis.zip

Here are a few suggestions to debug,

-Ensure you are truly getting 266MHz clock by probing the CK signal if available

-Double check the VREF voltage on both the processor side and the memory side.  This should be 0.6V

-Does the same issue occur on multiple boards?

-There are some slight differences between the CSV register dump and the register values in the tool.  Here are the differences that i found.  Can you fix these in your code to ensure the configuration is aligned with the tool output.

Address        CSV       Tool

0x4c000028 0x0f6ba22f 0x5F6BA22F

0x4c00002c 0x0f6ba22f 0x5F6BA22F

0x4c0000c8 0x50074be4 0x5007FA67

0x4c000200 0x04010040 0x00000040

0x4c000204 0x04010040 0x00000040

0x4c000208 0x00500050 0x00000050

0x4c00020c 0x00500050 0x00000050

0x4c000210 0x00500050 0x00000050

0x4c000214 0x00500050 0x00000050

0x4c000218 0x00500050 0x00000050

0x4c00021c 0x00500050 0x00000050

0x4c000220 0x00500050 0x00000050

0x4c000224 0x00500050 0x00000050

0x4c000228 0x00500050 0x00000050

0x4c00022c 0x00500050 0x00000050

0x4c000230 0x00350035 0x00000020

0x4c000234 0x00350035 0x00000020

0x4c000238 0x00350035 0x00000020

0x4c00023c 0x00350035 0x00000020

0x4c000240 0x00350035 0x00000020

0x4c000244 0x00350035 0x00000020

0x4c000248 0x00350035 0x00000020

0x4c00024c 0x00350035 0x00000020

0x4c000250 0x00350035 0x00000020

0x4c000254 0x00350035 0x00000020

0x4c000258 0x00000000 0x00000020

0x4c00025c 0x00000000 0x00000020

0x4c000260 0x00000000 0x00000020

0x4c000264 0x00000000 0x00000020

0x4c000268 0x00000000 0x00000020

0x4c00026c 0x00000000 0x00000020

0x4c000270 0x00000000 0x00000020

0x4c000274 0x00000000 0x00000020

0x4c000278 0x00000000 0x00000020

0x4c00027c 0x00000000 0x00000020

0x4c0002c8 0x01500150 0x00000000

0x4c0002cc 0x01500150 0x00000000

0x4c0002d0 0x01500150 0x00000000

0x4c0002d4 0x01500150 0x00000000

0x4c0002d8 0x01500150 0x00000000

0x4c0002dc 0x01500150 0x00000000

0x4c0002e0 0x01500150 0x00000000

0x4c0002e4 0x01500150 0x00000000

0x4c0002e8 0x01500150 0x00000000

0x4c0002ec 0x01500150 0x00000000

0x4c000318 0x00000077 0x00000000

0x4c00031c 0x00000077 0x00000000

0x44e1131c 0x0000000f 0x00000003

0x44e11460 0x00000001 0x00000101

 

Regards,

James

Hello 

Thanks for your advice.

I've checked as you commented.

-Ensure you are truly getting 266MHz clock by probing the CK signal if available

--> Correct(266Mhz)

-Double check the VREF voltage on both the processor side and the memory side.  This should be 0.6V

--> Yes. 600mV at both side

-Does the same issue occur on multiple boards?

--> checked 4borad but it show same output.

-There are some slight differences between the CSV

-> I used the same value as the generated output initially but it failed.
when reading the gel file code on online, it used different method(value) as follows.
Could you attach gel file for current spread sheet? I don't know how to get gel file.

Thanks

regards

//phy_reg_ctrl_slave_ratio
//10bits wide each slice, 3 slices concatenated
#define PHY_CTRL_SLAVE_RATIO 0x40

WR_MEM_32(EXT_PHY_CTRL_1 ,(PHY_CTRL_SLAVE_RATIO<<20)|(PHY_CTRL_SLAVE_RATIO<<10)|(PHY_CTRL_SLAVE_RATIO<<0));
WR_MEM_32(EXT_PHY_CTRL_1_SHDW ,(PHY_CTRL_SLAVE_RATIO<<20)|(PHY_CTRL_SLAVE_RATIO<<10)|(PHY_CTRL_SLAVE_RATIO<<0));

1665.AM43xx_EMIFconfig_HWlvl.gelI have attached a GEL which has the changes based on your  EMIF tool output.  Please give this a try.  One note: I am using a RL=4 instead of 8.

This is due to the data rate at which you are actually operating (LPDDR2-533), even though the device is capable of LPDDR2-1066 data rate.

Regards,

James

Thank you for advice in advance.

I have checked with additional memory test program.

When writing to the address 0x80000000 ~ 0x80000040 and reading the value again, the wrong value is always read every 0x10 offset.
ex)
write 0 at 0x80000000
write 1 at 0x80000004
write 2 at 0x80000008
write 3 at 0x8000000c
write 4 at 0x80000010
write 5 at 0x80000014
write 6 at 0x80000018
write 7 at 0x8000001c

read 0x80000004 --> 1
read 0x80000008 --> 2
read 0x8000000c --> 3
read 0x80000010 --> 0
read 0x80000010 --> 4 ( when read again, correct value is returned )
read 0x80000014 --> 5


I noticed there are some address line timing issues and I found that there is a trace length violation on our board.
CK : 23mm
CA2(Row2) : 17mm ( All others CA lines are 23mm)
The maximum ADDR_CTRL-CK skew is defined as 50 mils (1.27 mm) in the am4376 data sheet, but the current skew is 6 mm (236.2 mils).

Could you please guide the phy config parameter to adjust the timing?

Thanks
Regards