AM3352: Is there a timing requirement for total input power-on time Tr and VCC and communication interface?

Hi team,

             I have some questions about AM3352  timing sequence application:

1. Now the VCC5V is used as the total input in the design.

   How long does the Tr rise time need to be greater or less to ensure normal operation?

For example, when Tr > 1ms, you can work.

2. The communication interfaces used now are RX/TX and DP/DM.

Do VCC and RX/TX or DP/DM signals have strict power-on timing requirements?

For example: VCC5V power on first, it must be Delay 10ms before DP/DM can signal out.

thanks.