AM3359: Requirement added for Power-Supply Sequencing

Hi Biser-san,

Thank you for your reply.

Oh, it have been posted almost at the same time!

I will check the thread which you pointed out.

Best regards,

Daisuke

Hi Biser-san,

I checked the User's Guides for powering with PMIC for this added requirement.

The connections described in each of the following User's Guides can meet the added requirement.

TPS65910Ax User's Guide for AM335x Processors (Rev. F)
http://www.ti.com/lit/ug/swcu093f/swcu093f.pdf

Powering the AM335x, AM437x, and AM438x With TPS65218 (Rev. A)
http://www.ti.com/lit/ug/slvuaa9a/slvuaa9a.pdf

Powering the AM335x with the TPS65217x . (Rev. I)
http://www.ti.com/lit/ug/slvu551i/slvu551i.pdf

The connection described in the following User's Guide does not seem to meet the added requirement. Because the 1.8V power supply (DCDC2) connected to VDDS is powered up later than other 1.8V power supplies (LDO1 and LDO2).

Powering the AM335x With the TPS650250 (Rev. B)
http://www.ti.com/lit/ug/slvu731b/slvu731b.pdf

Is there any problem with this connection?

Should VDDS be connected to either LDO1 or LDO2?

Best regards,

Daisuke

Hi Daisuke,
Are you in the process of deciding a PMIC for your board design? And will you be using AM3359 at 600MHz? If you are considering the TPS650250 please know that this PMIC does not have adjustable output for the MPU so it is limited to OPP100 (300MHz to 600MHz depending on part number). If this is OK can you consider the TPS65216 as well? We're in the process of creating a user guide similar to the other guides you reviewed and it will be published next month.

Hi Ahmad-san,

Thank you for your reply. Sorry for my late reply.

Some of our customers have been designed board which the added requirement is not met, and most of them are in mass production. If multiple 1.8 V power supplies are used, the 1.8 V power supplies should be designed to be enabled at the same time, but the 1.8 V supplies have different rise times as well as the case of TPS650250.

Paul-san says the device may experience functional and reliability issues if the added requirement is not met: https://e2e.ti.com/support/processors/f/791/p/776564/2876975#2876975

I am concerned that the customers in mass production will have trouble if their design does not meet the added requirement.

Best regards,

Daisuke

Hi Daisuke,

Let me ask a colleague for comment. I am not very familiar with that PMIC solution.

Regards,
Ahmad

Hi Ahmad-san,

Thank you for your reply.

Have you gotten any comments from your colleagues?

If our customer design has multiple 1.8 V power supplies which are enabled at the same time but 1.8 V power supply with VDDS does NOT have the fastest rising time, should they redesign it?

Best regards,

Daisuke

Hello,

No I haven't gotten feedback yet. I pinged them again. Normally VDDS should ramp first. The most likely case is we determined the time delta between both 1.8V supplies is close enough that this was acceptable. Still need my colleague who designed this PMIC solution to confirm.

Regards,
Ahmad

Hi Ahmad-san,

Thank you for your reply.

I could understand that the time deltas between VDDS and other 1.8 V power supplies must be close enough to be acceptable. If there are other cases that multiple 1.8 V power supplies rise at the same time, I will confirm here whether it is acceptable.

Best regards,

Daisuke