TDA2: TDA2 5h AWR1243 frame over PCIe

Pass the VIP frames over PCI-e in real time?

Zach, what is the kind of data rates you are looking at? We have PCIe based storage to SSD which can potentially reach 400-420 MBytesps data rates. On Processor SDK 3.6 release there is a known issue for the PCIe speeds which limits the data rate to 1.6 Gbits ps, which is planned to be fixed in 3.7.

Thanks and Regards,
Piyali

Hi Piyali,

 

We are planning 30 frames per second of 128 doppler for the 1024 bits per chirp for 12 transmitter at the AWR1243 ADC resolution for 12 bits so per channel:

 

30 x 128 x 1024 x 128 x 12 x 12 = 566,231,040 bits per second for each channel.

 

We have been thinking in terms for a VIP frame with we assume had 4 channel interlaced per VIP frame.

 

So we need 4 times this number of bits per second. This is more then the 1.6 Gbps currently supported by PICe.

 

When will SDK 3.7 release? Is this same SDK of the TDA2-AWR1243 we are on hold for? What is the PCI-e

expected data rate at that time?

 

Can we plan on taking the VIP and separate it into channels and pass just on channel each way between the two TDA2 rather then the 4 channel VIP frame?

 

Regards,

Zach

Hi Zach,

To set your expectation correctly, we don't have application level SW for board to board communication over PCIe.

We have bare metal PCIe driver which can be used as your base to implement your own SW for the board to board communication.

Or, we have third party who can provide board-to-board PCIe solution.

The bare metal driver can transfer data between board at > 4Gbps.

The 1.6Gbps throughput Piyali mentioned was the PCIe SSD card write throughput using Linux SW with block driver.

We are working on improving the performance.

However, this is not applicable to your usage since it doesn't have support for board to board communication.

Regards,
Stanley

Thank you Stanley.

Please provide the third party who can provide board-to-board PCIe solution contact information?

Thank again,
Zach