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Linux/DRA71: Disable clock tree

user5787160
Expert 1190 points
Part Number: DRA71

Tool/software: Linux

Hi TI team,

We generated clock tree by using TI's CTT-Automotive-v1.0.0.5 tool, and we fount some clock we're not using and we want to disable them.

For example DPLL_IVA and Dvider_FUNC_48M_FCLK under DPLL_PER , can you advise how to do it.

Thanks.

BRs

Jeremy Zhang

  • 0
    TI__Expert 4885 points
    Hi, ,

    At its start the CTT uses the reset values of registers. Furthermore, it starts with the oscillator value set in CM_CLKSEL_SYS[2-0] SYS_CLKSEL (obligatory crystal for proper operation). The clocks you are mentioning are derived from the oscillator clock, that can't be stopped.

    The device architecture has hardware switches that are closed when a single module connected to them goes to Auto or Enable Mode set in the corresponding module register in MODULEMODE bit field.

    Actually at the start of the CTT the switch connected after DPLL_IVA is not closed, so the clock is not propagated to the rest of the clock tree.

    The clock after Divider_FUNC_48M_FCLKT can't be stopped because all muxes of UART1 to 10 (MUX_UARTx_GFCLK) and MUX_MCC3_FCLK and MUX_MMC4_FCLK, select either FUNC_192M_CLK or FUNC_48M_FCLK. The later is derived directly from FUNC_192M_CLK with no option to be disconnected.

    You can use View->Hide Others option from the menu bar to see where the clocks are propagated and if there are a way to disconnect all of the modules sourced by them.

    Just a side note

    Regards,
    Mariya
  • 0 in reply to Mariya Petkova
    TI__Expert 4885 points

    Just one side comment.

    You do not use the latest version of the package that is v.1.0.0.6. Several issues were fixed compared to v1.0.0.5. See CTT Release Notes for more information:

     

  • 0 in reply to Mariya Petkova
    Expert 1190 points
    Hi Mariya,

    Thanks for your reply.
    We are doing EMC test, to improve the test result we want to disable the clock we're not using, from your reply, some clock can't be disabled, then how about modifying the frequency?

    Below the list clock we recognize we're not using, please advise, thanks.
    Switch_DSP_GFCLK under DPLL_DSP
    Switch_PCIE_REF_CLK under DPLL_PCIE_REF
    Switch_PER_ABE_X1_GFCLK under DPLL_ABE
    DPLL_IVA
    DPLL_GPU
    Dvider_FUNC_48M_FCLK under DPLL_PER
    Dvider_FUNC_48M_FCLK under DPLL_PER
    DPLL_USB
    Switch_L3INIT_L4_GICLK under OCP2SCP1 /3
    USB1
    DCAN2


    BRs
    Jeremy Zhang
  • 0 in reply to user5787160
    TI__Expert 4885 points
    Hi, ,

    I am sorry, somehow I've missed your post. I will look at it later today or tomorrow.


    REgards,
    Mariya
  • 0 in reply to Mariya Petkova
    TI__Expert 4885 points
    Hi, ,

    You can use View->Hide Others option from the menu bar to see where the clocks are propagated and if there are a way to disconnect all of the modules sourced by them. The same option you can use to see where the clock is propagated and what will be its appropriate value.

    I am not entirely sure what do you ask for.

    For example, if you use the View->Hide Others option you will see that the output clock from Switch_DSP_GFCLK, namely DSP_FCLK, is sourced to DSP and Muxes - MUX_CLKOUTMUX0_CLK, MUX_CLKOUTMUX1_CLK, MUX_CLKOUT_MUX2_CLK, then to MUX_TIMER5,6,7,8_GFCLK and then to TIMER5,6,7,8. So, if you do not use DSP and you do not set the MUX_TIMERS to be sourced by derivative of the DSP_GFCLK will not be propagated.

    The output clock of Switch_PCIE_REF_CLK goes only to APLL_PCIE and if you don't use APLL_PCIE i don't see a problem.

    Furthermore, if you don't use a DPLL you can put it in its available low power mode.

    About modules as USB1, DCAN2, etc. If you don't power them they will be gated from the clocks. The control of the modules is done via MODULEMODE bitfield in the corresponding register in PRCM. See PRCM chapter of the Technical Reference Manual for modules registers.

    Hope this will help.

    Regards,
    Mariya