RTOS/PROCESSOR-SDK-AM437X: What's the difference in using MMU of example?

Hi,

Could you use the GPMC driver from Processor SDK RTOS on AM437x?

The SW is available: software-dl.ti.com/.../index_FDS.html .
The user guide: software-dl.ti.com/.../index_device_drv.html

The MMU setup is under ti\pdk_am437x_1_0_13\packages\ti\drv\gpmc\test\am437x\armv7\bios\gpmc_arm_evmam437x.cfg. If you want to use your own GPMC test code, you can create a SYSBIOS task and run it and measure the SRAM access timing.

Regards, Eric

Hi Eric,
I looked though the examples, I think that it is for the FLASH chip, not for the SRAM, the read and write operation will be big different. so I refered to the example "nand_app_read_write" in the sysbios_ind_sdk_2.1.0.1, and transplanted its hardware driver. now the code can work orderly. but when I transplanted this code to TI-RTOS( example Nimu_BasicExample_skAM437x_armExampleproject), I found the delay.
do you the code for SRAM operation in SDK RTOS? or any advice?
can you tell me the different between the function SDKMMUInit() and the function MMUConfigAndEnable() and CACHEEnable()?

zhuangbin,

sysbios_ind_sdk_2.1.0.1 was migrated into Processor SDK RTOS. In Processor SDK RTOS, the GPMC interface for AM335x or AM437x are for flash devices, sorry we don't have any code examples for SRAM. But as you already developed the GMPC to SRAM code and proved working, the only thing you need to do is get the correct cache and MMU setting.

As mentioned earlier, you can refer to ti\pdk_am437x_1_0_13\packages\ti\drv\gpmc\test\am437x\armv7\bios\gpmc_arm_evmam437x.cfg:

* ================ Cache and MMU configuration ================ */

var Cache = xdc.useModule('ti.sysbios.family.arm.a9.Cache');
Cache.enableCache = true;
Cache.configureL2Sram = false;//DDR build

var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu');
Mmu.enableMMU = true;

/* Force peripheral section to be NON cacheable strongly-ordered memory */
var peripheralAttrs = {
type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
tex: 0,
bufferable : false, // bufferable
cacheable : false, // cacheable
shareable : false, // shareable
noexecute : true, // not executable
};

/* Define the base address of the 1 Meg page the peripheral resides in. */
var prcmBaseAddr = 0x44df2800;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(prcmBaseAddr,
prcmBaseAddr,
peripheralAttrs);

var i2c0BaseAddr = 0x44e0b000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(i2c0BaseAddr,
i2c0BaseAddr,
peripheralAttrs);

/* Define the base address of the 1 Meg page the peripheral resides in. */
var uart3BaseAddr = 0x481a6000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(uart3BaseAddr,
uart3BaseAddr,
peripheralAttrs);

/* Define the base address of the 1 Meg page the peripheral resides in. */
var gpmcBaseAddr = 0x50000000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(gpmcBaseAddr,
gpmcBaseAddr,
peripheralAttrs);

/* Define the base address of the 1 Meg page the peripheral resides in. */
var elmBaseAddr = 0x48080000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(elmBaseAddr,
elmBaseAddr,
peripheralAttrs);


Also, create a task function, and add all your main functions as a task. Then test it.

Regards, Eric

Hi Eric，

I compared the gpmc_arm_evmam437x.cfg with the .cfg and MMU init code(the function SDKMMUInit()) of NIMU_BasicExample_skAM437x_armExampleproject, I thank that they perform the same functions.

and I want you to notice the different initialization parameters of the MMU in the example tcpecho of sysbios_ind_sdk_2.1.0.1,it call the mmu init function in the example_utils_mmu.c with the parameter as follow:

mmuMemRegionConfig_t regionSRAM =
            {
                0x1000000,
                1,
                1*MEM_SIZE_MB,
                MMU_MEM_ATTR_DEVICE_NON_SHAREABLE,
                MMU_CACHE_POLICY_WT_NOWA,
                MMU_CACHE_POLICY_WT_NOWA,
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE
            };

these parameter may not be used in the Processor SDK RTOS init codes.

I understand what you mean. I will use the API to initialize the GPMC, and write my own program to read and write SRAM.

but I  researched the GPMC setting parameters GPMC_v1_HwAttrs_s in the GPMC_v1.h, many of these parameters are not well understood.

As I mentioned earlier in the init code, the SRAM CS is connected to the gpmc_csn1, physical base address is 0x1000000, address space is 16MBytes, 

How to set these parameters of GPMC_v1_HwAttrs_s?

Hi Eric，
In the cfg, do I need to setup MMU for the SRAM baseaddress( 0x100000)?

Hi,

My SRAM baseaddress is 0x1000000. in the .cfg file, do I need to add the codes as follow:

var peripheralBaseAddr = 0x1000000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(peripheralBaseAddr,   peripheralBaseAddr,  peripheralAttrs);

I do it, and the results is same as the one of NIMU_BasicExample_skAM437x_armExampleproject, there is a about 260ns delay after each access.

Hi,

>>>var peripheralBaseAddr = 0x1000000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
>>>>

What is the peripheralAttrs for this?

Regards, Eric

Hi,

You wanted this setup using SYSBIOS
mmuMemRegionConfig_t regionSRAM =
{
0x1000000,
1,
1*MEM_SIZE_MB,
MMU_MEM_ATTR_DEVICE_NON_SHAREABLE,
MMU_CACHE_POLICY_WT_NOWA,
MMU_CACHE_POLICY_WT_NOWA,
MMU_ACCESS_CTRL_PRV_RW_USR_RW,
FALSE
};

I found this E2E: e2e.ti.com/.../1395492

In order to mark a memory page as write-through cacheable, you will need to update that page's corresponding MMU entry. To change the cacheability of a page to outer and inner write-through no write-allocated, set the TEX[2:0] attribute for the page to 0, cacheable to true and bufferable to false. Here's some untested code showing how to do this using SYS/BIOS APIs:

Mmu_FirstLevelDescAttrs attrs;
Mmu_initDescAttrs(&attrs);

attrs.type = Mmu_FirstLevelDescType_SECTION;
attrs.tex = 0;
attrs.cacheable = true;
attrs.bufferable = false;

attrs.shareable = false;

You can refer to ARM architecture document static.docs.arm.com/.../DDI0406C_C_arm_architecture_reference_manual.pdf. B3.8.2 Short-descriptor format memory region attributes, without TEX remap for the combination of TEX, B-bit and C-bit to achieve Outer and Inner Write-Through, no Write-Allocate.

Regards, Eric

Hi Eric,

I change the settings as what you tell me. now it is ok.

Thank you very much!

I'd like to know the relationship of structural parameter settings between mmuMemRegionConfig_t and Mmu_FirstLevelDescAttrs.

as follow:

/** \brief  Define DDR memory region. DDR can be configured as Normal memory  with R/W access in user/privileged modes. */
mmuMemRegionConfig_t regionDdr =
            {   
                START_ADDR_DDR,
                NUM_SECTIONS_DDR,                            /* Number of pages */
                1U*MEM_SIZE_MB,                                   /* Page size - 1MB */
                MMU_MEM_ATTR_NORMAL_NON_SHAREABLE,
                MMU_CACHE_POLICY_WB_WA,            /* Inner */
                MMU_CACHE_POLICY_WB_WA,            /* Outer */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE /* Non Secure memory */
            };

/** \brief Define OCMC RAM region. */
mmuMemRegionConfig_t regionOcmc =
            {   
                0,
                NUM_SECTIONS_OCMC, /* Number of pages */
                1U*MEM_SIZE_MB, /* Page size - Min 1MB */
                MMU_MEM_ATTR_NORMAL_NON_SHAREABLE,
                MMU_CACHE_POLICY_WT_NOWA, /* Inner */
                MMU_CACHE_POLICY_WB_WA, /* Outer */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE /* Non Secure memory */
            };

/** \brief Define Device Memory Region. The region between OCMC and DDR is  configured as device memory, with R/W access in user/privileged  modes. Also, the region is marked 'Execute Never'.
 */
mmuMemRegionConfig_t regionDev =
            {   
                START_ADDR_DEV,
                NUM_SECTIONS_DEV,                    /* Number of pages */
                1U*MEM_SIZE_MB,                          /* Page size - 1MB */
                MMU_MEM_ATTR_DEVICE_SHAREABLE,
                MMU_CACHE_POLICY_WB_WA,     /* Inner - Invalid here */
                MMU_CACHE_POLICY_WB_WA,     /* Outer - Invalid here */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE                                                /* Non Secure memory */
            };

mmuMemRegionConfig_t regionQspi =
            {
                START_ADDR_QSPI,
                NUM_SECTIONS_QSPI,                      /* Number of Pages */
                1U*MEM_SIZE_MB,                             /* Page size - 1MB */
                MMU_MEM_ATTR_DEVICE_NON_SHAREABLE,
                MMU_CACHE_POLICY_WB_WA,       /* Inner - Irrelevant here */
                MMU_CACHE_POLICY_WB_WA,       /* Outer - Irrelevant here */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE                                                  /* Non Secure memory */
            };

How should I set relevant parameters of the Mmu_FirstLevelDescAttrs  in response to the above parameter settings?

Hi,

For the structure defined inside mmuMemRegionConfig_t:

typedef struct region {
uint32_t startAddr; /**< Start Address of the page */
uint32_t numPages; /**< Number of Pages in the region */
uint32_t pgSize; /**< Size of the Page (in bytes) */
mmuMemAttr_t memAttrib; /**< SO, Device, Normal (shareable ?) */
mmuCachePolicy_t innerCachePolicy; /**< Applicable for normal mem only */
mmuCachePolicy_t outerCachePolicy; /**< Applicable for normal mem only */
mmuAccessCtrl_t accessCtrl; /**< Access Permissions for the page */
uint32_t isMemSecure; /**< Secure or non secure (TRUE or FALSE) */
}

startAddr is where it starts, numPages*pgSize determine the length. In the SYSBIOS, the first Level descriptor size is 1GB, the second level descriptor size is 4MB.

For the rest fields, please read the ARM architecture document section B3.7 and B3.8 for the relationship.

Regards, Eric

Hi,
I want to know how to set the parameters of Mmu_FirstLevelDescAttrs to achieve the setting effect of the parameters of mmuMemRegionConfig_t.
now I had known that if we set the parameters of Mmu_FirstLevelDescAttrs:
attrs.type = Mmu_FirstLevelDescType_SECTION;
attrs.tex = 0;
attrs.cacheable = true;
attrs.bufferable = false;
attrs.shareable = false;

it is same as the parameters setting of mmuMemRegionConfig_t:
1*MEM_SIZE_MB,
MMU_MEM_ATTR_DEVICE_NON_SHAREABLE,
MMU_CACHE_POLICY_WT_NOWA,
MMU_CACHE_POLICY_WT_NOWA,
MMU_ACCESS_CTRL_PRV_RW_USR_RW,
FALSE

I don't know the relationship between the two sets of parameters.
if the changing the parameters setting of mmuMemRegionConfig_t, I do not know how to set the parameters of Mmu_FirstLevelDescAttrs, like as follow:
mmuMemRegionConfig_t regionDdr =
            {   
                START_ADDR_DDR,
                NUM_SECTIONS_DDR,                            /* Number of pages */
                1U*MEM_SIZE_MB,                                   /* Page size - 1MB */
                MMU_MEM_ATTR_NORMAL_NON_SHAREABLE,
                MMU_CACHE_POLICY_WB_WA,            /* Inner */
                MMU_CACHE_POLICY_WB_WA,            /* Outer */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE /* Non Secure memory */
            };

or
mmuMemRegionConfig_t regionOcmc =
            {   
                0,
                NUM_SECTIONS_OCMC, /* Number of pages */
                1U*MEM_SIZE_MB, /* Page size - Min 1MB */
                MMU_MEM_ATTR_NORMAL_NON_SHAREABLE,
                MMU_CACHE_POLICY_WT_NOWA, /* Inner */
                MMU_CACHE_POLICY_WB_WA, /* Outer */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE /* Non Secure memory */
            };

or
mmuMemRegionConfig_t regionDev =
            {   
                START_ADDR_DEV,
                NUM_SECTIONS_DEV,                    /* Number of pages */
                1U*MEM_SIZE_MB,                          /* Page size - 1MB */
                MMU_MEM_ATTR_DEVICE_SHAREABLE,
                MMU_CACHE_POLICY_WB_WA,     /* Inner - Invalid here */
                MMU_CACHE_POLICY_WB_WA,     /* Outer - Invalid here */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE                                                /* Non Secure memory */
            };
or
mmuMemRegionConfig_t regionQspi =
            {
                START_ADDR_QSPI,
                NUM_SECTIONS_QSPI,                      /* Number of Pages */
                1U*MEM_SIZE_MB,                             /* Page size - 1MB */
                MMU_MEM_ATTR_DEVICE_NON_SHAREABLE,
                MMU_CACHE_POLICY_WB_WA,       /* Inner - Irrelevant here */
                MMU_CACHE_POLICY_WB_WA,       /* Outer - Irrelevant here */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE                                                  /* Non Secure memory */
            };
I want to know how to set the corresponding parameters of Mmu_FirstLevelDescAttrs.