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RTOS/TDA2P-ACD: LCD Horizontal sync

Stefan Koncar
Genius 3050 points
Part Number: TDA2P-ACD

Tool/software: TI-RTOS

Hi,

I’m using TDA2p custom board and PSDK 3.03. I’m using LCD output and I'm facing some strange data corruption.

LCD pins on TDA2p are connected to Parallel-to-CSI converter. Parallel-to-CSI converter doesn't have DE signal, only HSYNC, VSYNC, PCLK and DATA (24 lanes).

Some typically 1080p@30fps timings for LCD are as shown below.

pVInfo->mInfo.pixelClock = 74250U;
pVInfo->mInfo.fps = 30U;
pVInfo->mInfo.hBackPorch = 88U;
pVInfo->mInfo.hSyncLen = 44U;
pVInfo->mInfo.hFrontPorch = 148U;
pVInfo->mInfo.vFrontPorch = 4U;
pVInfo->mInfo.vSyncLen = 5U;
pVInfo->mInfo.vBackPorch = 36U;

This means DE signal time will be: 88 + 44 + 148 = 280 pixel clock periods. Considering, device connected with TDA2p doesn't have DE input signal, only HSYNC, my horizontal timing should look like this:

pVInfo->mInfo.hBackPorch = 1U;
pVInfo->mInfo.hSyncLen = 255U;
pVInfo->mInfo.hFrontPorch = 1U;

According to TDA2p TRM max horizontal synchronization pulse width is 255. This will make HSYNC and DE signals width equal. But, this pulse width is shorter than recommended value (280 pixel clock periods).

Could this this produce data corruption? Is there some minimum required HSYNC width on TDA2p side?

Best regards,

Stefan.

  • 0
    TI__Guru**** 475655 points
    Stefan,

    But in this case, why don't you connect DE output from TDA2px as hsync input to parallel to CSI converter? this will be better solution.
    Yes, HSW is limited to 256 clock pulses.. This is HW limitation.. Also please note that HFP and HBP cannot be 0 clock pulses.. The minimum value for both of them is 1 clock cycle..

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Genius 3050 points
    Brijesh,

    Yes, that was my idea. But, I don't want to do that if this is not cause of my problem. Still, this require change in my PCB.
    Also, I'm aware that HFP and HBP can not be 0, I set them to 1.
    So, you think that this lower timing can be problem?

    Best regards,
    Stefan.
  • 0 in reply to Stefan Koncar
    TI__Guru**** 475655 points
    Stefan,

    It could be problem if hsync with smaller pulse size is used as de. It all depends on the receiver..
    I guess the Parallel to SDI encoder will probably just convert to serial format, but if the connected LCD supports only standard timings and cannot accept any variations in timing, it would not work..

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    TI__Guru**** 475655 points
    Hi Stefan,

    Any further question on this? I am closing this thread, due to no activity.
    We can reopen the thread if you have any further questions..

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Genius 3050 points
    Brijesh,

    After swapping HSYNC and DE lanes on PCB all data is received correctly. This 2 additional clock pulses have caused appearance of 4 byte of zero (2 px green line) at the beginning of each line.
    Thank you on your time.

    Best regards,
    Stefan.