AM4372: About DDR3 Layout and Timing setting issue

yimin bai34

Genius 4755 points

Part Number: AM4372

Hi Sir

We did DDR test and found below test failed issue in high 16bit.

And we reviewed our layout and found the DDR fly-by is in contrast like below.

In normal, U20 should be close to CPU. But our design is U21 be close to CPU.

Do you have any suggestion about how to modify DDR3 parameters like write-leveling ?

Yimin

over 6 years ago

0 Brad Griffis over 6 years ago

TI__Guru*** 125430 points

Have you filled out the AM437x DDR spreadsheet that goes along with the EMIF Tools app note:

http://www.ti.com/lit/sprac70

Please attach your completed spreadsheet to this thread.

Also, please download this utility for dumping the DDR-related registers:

git.ti.com/.../am43xx-ddr-analysis.dss

Directions on running the script are here:

git.ti.com/.../README

The script will output two files to your desktop: a *.txt and *.csv. Please zip and attach them.

0 Brad Griffis over 6 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

Please also provide details on what software you're using, RTOS SBL, u-boot, etc. including the version.

0 yimin bai over 6 years ago in reply to Brad Griffis

Intellectual 265 points

Hi Sir

We used latest Linux SDK for development

Processors

Processors forum

AM4372: About DDR3 Layout and Timing setting issue