RTOS/TMS320C6678: NDK Configuration for Two External PHY

Hi,
I have tried single PHY under NDK, Which also not working in our custom board. Please give step by step comprehensive idea about the NDK implementation for my case. I already read related documents. So do not give any documents. Please give what are the changes I have to make in the files and what are the files I have to include.

my questions:

1. Is only one function call ( EMACInit_Core() ) enough to start NDK configuration ?. only one file ( nimu_eth.c ) is related to ndk implementation?
2.What are the functions I have to change ?
3. In that example ( NIMU_emacClientExample_EVMC6678C66BiosExampleProject) where that EMACInit_Core() was called ?. In my project where I have to call EMACInit_Core() ? (which step)
4. STKEVENT_Handle emac; if I call EMACInit_Core(emac), I have warning like that "#551-D variable "emac" is used before its value is set Ethernet_config.c".
5. I have made PHY configuration via MDIO. So I changed Init_MDIO(), Is it correct ? I attached code below:

void Init_MDIO (uint8_t phy_addr)
{
//Enable MDIO Control
hMdioRegs->CONTROL_REG |= 0x410000ff;

// Register 18 = 0 (disable all interrupts
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR,18) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));


// Register 9 = 0x1F00
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 9) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x1B00;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Register 0 = 0x9140
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 0) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x9140;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Register 29 = 7 page 7
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0007;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Register 30 = 0x0808
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0808;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Register 29 = 0x10 page 16
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x10;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Register 30 = 0x005A
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0042;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Register 29 = 0x12 page 18
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x12;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Register 30 = 0x8241
hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) |
CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) |
CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) |
CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x8901;
// Wait for MDIO state machine finishing
while (CSL_MDIO_isUserAccessPending (0));

// Disable MDIO Control
hMdioRegs->CONTROL_REG &= 0xBFFFFFFFF;

//NIMU_testLog ("PHY %d configured in MARVELL external loopback mode \n",phy_addr);

/* There is nothing to be done for C6678 EVM */
return;
}

Currently I am using following versions of TI Tools.
CCS v8.2
TI-RTOS - ti-processor-sdk-rtos-c667x-evm-05.01.00.11
BIOS - bios_6_73_00_12
Device - TMS320c6678,
PDK - pdk_c667x_2_0_11,
NDK - ndk_3_40_01_01,



Thank you in advance for your support.
Mohan.

Hi,

In that NDK example ( NIMU_emacClientExample_EVMC6678C66BiosExampleProject) I have edited the code in EMACInit_Core=> Init_Cpsw() function as per our PHY configuration. Now the PHY was configured. The problem is testing the example project. I have checked Ethernet communication using ping command but it didn't work. Currently the example working on DHCPC mode but I want to use static IP, where I have to change that things. I don't know how to test the example project. Please give some idea (or) utility to test the example project.

project name: NIMU_emacClientExample_EVMC6678C66BiosExampleProject.

console output:
---------------------
CP/IP Stack Example Client
Configuring DHCP client
Service Status: DHCPC : Enabled : : 000
Service Status: Telnet : Enabled : : 000
Service Status: HTTP : Enabled : : 000

Hi,
Now I am trying to configure single PHY only which also not working. I have used another example "Hello World"(NIMU_emacExample_EVMC6678C66BiosExampleProject) In which they are using static IP. I have given IPaddress : 192.168.1.2 and subnet mask : 255.255.255.0. I have connected my PC to custom board with same subnet mask. ping is not happened between there. I am also tried on Evaluation board ( TI TMS320C6678 EVM Board ). I just import your hello world example and edit the IP address and subnet mask. This case also not working. Ping was not send. So please give proper steps to port NDK on evaluation board and tell how to test your NDK example.


Regards,
Mohan.

Thank for your reply,
actually I don't know how to test that example. any changes we have to make in existing code ?. Please guide me step by step to run example project.

Thanks yordan,
Now the example code has worked properly. I want to port NDK in our project. I have doubt in your example, where the PHY Initializations are made?. I mean PHY enable and SGMII_Init() these things. What are the changes I have to made?.


Thanks,
Mohan.