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RTOS/AM5728: ow to write the appropriate MMU setting for using GPMC

matusan
Guru 10235 points

Part Number: AM5728

Tool/software: TI-RTOS

Hello, TI Experts,

 

Our customer sent us question about MMU seting for GPMC with PROCESSOR-SDK-RTOS-AM57X.

They tried to add GPMC function to EcMaster product based on http://www.ti.com/lit/ug/tidubz1b/tidubz1b.pdf

 

But they found exception when GPMC-area (0x08000000..0x0800FFFF) accress is occrred.

They thought some additional MMU setting is needed in *.cfg file (EcMaster.cfg).

 

Question:

  Could you tell us how to write the appropriate MMU setting for using GPMC-area(0x08000000..0x0800FFFF) access.

 

We' like to attach EcMaster.cfg as their project *.cfg file.

We would also appreciate if you check the MMU setting "EcMaster.cfg" and tell us how to modify this cfg file.

 

Best regards,

4401.EcMaster.cfg

  • 0
    TI__Guru* 95265 points
    Hi,

    You are trying to access memory 0x0800_0000, you need to configure the first level MMU covering 0x0000_0000 to 0x4000_0000, then second level MMU to cover 0x0800:0000 to ?

    See the same issue: e2e.ti.com/.../579072

    Regards, Eric
  • 0 in reply to lding
    Guru 10235 points
    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.

    We can success to access GPMC-area(0x08000000..0x0800FFFF) by adding below description
    to our .cfg file based on the E2E thread from your guide.
    Thank you!

    --
    var peripheralAttrs = new Mmu.DescriptorAttrs();
    Mmu.initDescAttrsMeta(peripheralAttrs);
    peripheralAttrs.type = Mmu.DescriptorType_TABLE;
    Mmu.setFirstLevelDescMeta(0, 0, peripheralAttrs);

    peripheralAttrs.type = Mmu.DescriptorType_BLOCK;
    peripheralAttrs.noExecute = true;
    peripheralAttrs.accPerm = 0;
    peripheralAttrs.attrIndx = 4;
    Mmu.setMAIRMeta(4, 0x00);

    var peripheralBaseAddr = 0x08000000;
    Mmu.setSecondLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
    --

    I have a question like below;
    - "peripheralAttrs.attrIndx = 4" indicate MAIR_1.Attr4[7:0] in "16.5.12 SMMU_CBn_MAIRm,
    Memory Attribute Indirection Registers" of the below document.
    infocenter.arm.com/.../IHI0062D_c_system_mmu_architecture_specification.pdf
    - "Mmu.setMAIRMeta(4, 0x00)" means that MAIR_1.Attr4[7:0] can be configured to "0x00".

    Is this understanding correct?

    Best regards,
  • 0 in reply to matusan
    TI__Guru* 95265 points
    Hi,

    Good to know you can access the GPMC region!

    "Mmu.setMAIRMeta(4, 0x00)" means that MAIR_1.Attr4[7:0] can be configured to "0x00". >>>> Yes, that is correct.

    Regards, Eric
  • 0 in reply to lding
    Guru 10235 points

    Hi,

    Thank you very much for your kindness.

    I really appreciate your help.

    Best regards,