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Compiler/TCI6636K2H: CCS version 6.1

Part Number: TCI6636K2H

Tool/software: TI C/C++ Compiler

I am testing QDMA, I found it works sometimes but not always. Then I found the address of some registers were not correct. See the code below (Initialisation was copied from examples in MCSDK and not attached here. )

Case it didn't work: when the loop1 variable is defined inside the for loop, then the address of TPCC_IPR will be changed to something else. if I move loop1 to above the for loop, then it works.

I couldn't understand the reason, and feel very unsafe with bunch of code I have developed since I never know this is not OK. 

BTY: optimisation was disabled.

1) Code

int32_t loop;
//int loop1; //
for (loop=0; loop<8; loop++)
{
int loop1; // Doesn't work, DMA register address has been changed.
System_printf("1st TPCC_IPR- %x\n", &(tDmaHanles_hEdmaModule->regs->TPCC_IPR));

for (loop1=0; loop1<6; loop1++)
{
gafBuf_DDR3[loop1] = (loop1+1)*1.0f;
}

System_printf("2nd TPCC_IPR- %x\n", &(tDmaHanles_hEdmaModule->regs->TPCC_IPR));

do
{
CSL_edma3GetHwStatus(tDmaHanles_hEdmaModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntr);
} while (!(regionIntr.intr & tccPing));
System_printf("gafBuf_L2: %f, %f\n", gafBuf_L2[0], gafBuf_L2[1]);

/* Clear pending interrupt */
CSL_edma3HwControl(tDmaHanles_hEdmaModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, &regionIntr);

if (loop < 8-1)
{
CSL_edma3ParamWriteWord(hParamPing,7,1);
}

gafBuf_L2[0] = 0.0f;
gafBuf_L2[1] = 0.0f;
}

2)Output

1st TPCC_IPR- 2741068
2nd TPCC_IPR- 106e

 

 

  • Hi,

    Is loop1 just a counter for the number of loops in the second for loop? or is it somehow tied to the TPCC_IPR? I see gafBuf_DDR3[loop1] = (loop1+1)*1.0f; but from the code you've shared it doesn't seem linked to the TPCC_IPR address.

    Then if loop1 is defined within the for loop:
    for (loop=0; loop<8; loop++)
    {
    int loop1; // Doesn't work, DMA register address has been changed.
    System_printf("1st TPCC_IPR- %x\n", &(tDmaHanles_hEdmaModule->regs->TPCC_IPR));

    for (loop1=0; loop1<6; loop1++)

    you actually define it each time the for (loop=0; loop<8; loop++) spins (8 times total).. I think this is not necessary.

    Best Regards,
    Yordan

  • Yes, loop1 is just a counter. gafBuf_DDR3 is a normal buffe in DDR3.

    This is a piece of test code, I met this problem before I had added useful code yet. I really want to know why it didn't work, otherwise it is hard to feel safe with my code.

    Thanks!

    Zijun

  • Hi,

    This doesn't seem related to IPR address change. Could you enable the Registers & Variables views (from CCS menu: View -> Variables & View -> Registers) then execute code step by step using breakpoints to locate the exact fragment of code (function) where the register address changes. Also can you share your .cfg & linker.cmd files?

    Best Regards,
    Yordan
  • config.cfgSorry, I don't have the enviroment which can debug with CCS.

    Here is the contents in .cmd file:

    SECTIONS

    {

       .datal2   > L2SRAM

       .datal3:    > MSMCSRAM

       .dataDDR: load > DDR3, type = NOLOAD

    }

  • Hi,

    On first glance the .cfg seems ok. I am not sure how I can help without having the tools to debug this further (connecting your board to CCS via JTAG).
    What we usually recommend customers is to try the same example on TI EVM (in your case K2H EVM) and see if this is reproducible, could you do that?

    Best Regards,
    Yordan