Tool/software: Code Composer Studio
Can you please clarify how Data RAM 0 and Data RAM 1 for PRU0 and PRU1 in C6748?
Each is 512 bytes in size. Each PRU has (or at least has access to) both Data RAM 0 and 1. What are the limitations? Are there actually three 512 byte RAM's and one of them is shared between the PRU's?
Thanks.
Peter,
Please see the PRUSS Local Memory Map in Section 12.8.1.1 of the TMS320C6748 TRM (http://www.ti.com/lit/pdf/spruh79):
As the note below the tables states: Data RAM 0 is meant to be the primary data memory for PRU0 and Data RAM 1 is meant to be the primary data memory for PRU1.
Each PRU can access its primary data memory at address 0x00000000. So when PRU0 makes a local access to 0x00000000 it is accessing Data RAM 0 and when PRU1 makes a local access to 0x00000000 it is accessing Data RAM 1.
If a PRU would like to access the Data RAM of the OTHER PRU then it would use address 0x00002000. For instance, PRU0 accessing Data RAM 1 would use 0x00002000 and PRU1 accessing Data RAM 0 would use address 0x00002000.
There are two 512 byte memories.
Jason Reeder
