TMS320C6654: Typical power consumption of C6654, C6672 and C6674?

Hi,

Sorry for the delay, this has been forwarded to the design team and is being looked at.

Best Regards,
Yordan

Thanks,

I was able to fill the tool and this is what I get. See attached. Does it look correct? It allows me to set the DDR to 667 MHz. I thought the maximum on the device is DDR-1066 or 533 MHz?

C6654_Power_Spreadsheet_Rev_2_0_WB-ADS.zip

Ramgopal,

The C6652 and C6654 devices are one rated for DDR3-1066 operation.  The pin-compatible devices C6655 and C6657 support DDR3-1333 operation.  It appear that this spreadsheet was not updated to reflect the lower limit.  Be sure to not set the DDR clock speed above 533 for the C6654.

Please refer to SPRABI5 for instructions on populating this spreadsheet. The % Utilization values entered are too high.  For instance, refer to the paragraph copied below:

% Signal Processing (SP) Utilization is used to represent scenarios with high levels of CorePac activity. This corresponds to the case in which all eight instructions fetched by the CorePac are executed in parallel each for CorePac clock cycle, resulting in all eight functional units being active every cycle. Few CorePac algorithms will achieve 100% CorePac utilization because this requires execution of all eight function units every cycle with no stalls. Even intense applications do not spend all of the time executing such highly parallel code.

A realistic value for % SP is 27% for well written C-code with the optimizer enabled.  As indicated, 100% would have all eight functional units active on every clock cycle allowing for no bus stalls.  Even carefully written assembly code operating from program stored in L1 cache and data stored in L2 memory will only achieve about 50% and that can only occur for very short periods of time.  Similarly, DDR3, EMAC, Timer and UPP will not be used at 100%.

Tom

Thank you,
I made all the 100% as 50%, SP as 27% and CC as 30%. The CVDD supply I plan to use is a TI recommended 5A supply so should be more than enough.
Thanks!
Divakar

Tom,
I am working on designing a power supply for CVDD input to TMS320C6654. The excel calculator says it is around 2A. Do I need 2 x 470 uF and 2 x 220 uF recommended in the hardware design guide for bulk caps? This is a low end device as opposed to C6678 so I am assuming the hardware design guide is a general recommendation. The DC-DC I am using is a LTM4625 with VID control and the output caps recommended in LTM4625 is of the order of 200 uF. How much bulk caps are needed at CVDD input.

Also, should the default value of LM10011 on power up be strapped for 1.1V? I saw some posts where someone set it to 1.05V and the datasheet example in LM10011 also sets it to 1.05.

Just making sure it must be set to 1.1V

Ramgopal,

Your assessment of the bulk decoupling required is correct.  You must calculate the required amount and validate it.  The Hardware Design Guide (SPRABI2) discusses this calculation.

This bulk capacitance will affect the control loop on the power supply so this must be considered as well.  Webench is available for supplies from TI such as those recommended in the attached PPT.

Regarding the AVS start-up voltage, refer to table 5.3 in the Data Manual and footnote 4 below it:

(4) The initial CVDD voltage at power on will be 1.1V nominal and it must transition to VID set value immediately after being presented on
VCNTL pins. This is required to maintain full power functionality and reliability targets ensured by TI.

Tom

6406.Power Managment for C667x and C665x_041812b.pptx