Even though I marked this thread as not having a problem, that's mainly because I have not started designing the circuitry in the KiCAD software just yet, I am figuring out how to make the AM5708 SOC work to my advantage - I have the particular processor in my possession now.
Last time I asked about the alternative to the TI-RTOS on the C6k VLIW processor, it was mentioned that TI-RTOS is mandatory (I was kind of hoping to use FreeRTOS or Zephyr RTOS with some software tricks I may attempt to use to squeeze a bit more performance out of the DSP if that's possible at all).
So, the software trick I mentioned is that I am thinking of implementing the dynamic trace scheduling (or dynamic tree fanout scheduling basing on the branch prediction) as a possibility (I was reading up on the research papers on turning the VLIW processors into soft defined out-of-order processors to gain a bit more performance in dealing with the demanding software which could be useful, however I have to figure out what makes the C6k processors, especially the C66x DSP, tick). I am wondering if any VLIW compilers, including the GCC, impose strict ordering (in a way that hardware / software exploitation is ignored to enforce in-order execution), if they do impose the strict execution ordering, I will have to figure out the option that I have regarding whatever's on the processor die (the Cortex A15 is of course an out-of-order processor, however I am not 100% sure how good is its FPU, even though it is supposed to be a superscalar VFPv4 FPU, so I may have to use the DSP due to the vector nature of the particular VLIW processor in question), as I am planning on rolling my own portable oscilloscope / logic analyzer combo, so it need to be able to crunch the ADC (analog to digital converter) matrix data while also saving on battery power (ie. VLIW processor's core frequency can be throttled down without imparting too much performance impact).
