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TDA2EVM5777: Enabling DSP Cache using PDK software

Jmg65
Expert 1365 points

Part Number: TDA2EVM5777

Hello,

We're developing a program to run inside one of the TDA DSP cores using PDK_01.10.02.07. We need to have the program executed as quickly as possible and wanted to use cache but were unable to find any similar examples in the PDK.


How do we configure the DSP1 core to use L1 and L2 cache for both Instructions and data?

Is the dsp MMU required to use cache and what functions are necessary to enable and configure it properly?

Are there any examples you can point to that would help answer the above?   

Thank you

  • 0
    TI__Guru 55685 points
    Hi,

    You can refer to <pdk>\packages\ti\csl\example\ecc\ecc_test_app\main_c66x.c or <pdk>\packages\ti\csl\example\xmc_mpu\xmc_mpu_test_app\xmc_mpu_app.c.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    TI__Mastermind 42515 points
    Hi,

    in addition to what Rishabh pointed, you can check "TMS320C66x DSP Cache" user guide for familiarization with DSP cache:
    www.ti.com/.../sprugy8.pdf

    Regards,
    Yordan
  • 0 in reply to Rishabh Garg
    Expert 1365 points

    Hello Rishabh,

    Thank you for your reply. As part of the DSP function we will need to scale through large datasets, larger than all cache available. How would that function? Do we need to enable the dsp MMU to achieve that and if  yes, are there any examples?

    Thanks you. 

  • 0 in reply to Jmg65
    TI__Guru 55685 points
    Hi,

    Cache will automatically flush the older entries and have new entries.
    For MMU example you can refer to PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\csl\example\mmu\mmu_tlb_twl.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Expert 1365 points
    Hello Rishabh

    I've been going over the examples you listed trying to achieve some some speed benefit from using cache. Unfortunately no success yet. Using only the approach in the XMC example has no noticeable difference in software execution time. You mentioned cache will automatically flush the older entries and have new ones so not sure why the XMC example doesn't provide a speedup.

    I have tried but still not sure how the MMU example needs to get updated to make use of cache space automatically. On the a15 that was a MAIR setting but I don't see any such function in this DSP MMU example.

    Thanks.
  • 0 in reply to Jmg65
    TI__Mastermind 30245 points
    Hi,

    You need to add below:

    /* Configure Cache size of L1D */
    retVal = DSPICFGCacheEnable(SOC_DSP_ICFG_BASE,
    DSPICFG_MEM_L1D,
    DSPICFG_CACHE_SIZE_L1_MAX);
    /* Configure Cache size of L1P */
    retVal = DSPICFGCacheEnable(SOC_DSP_ICFG_BASE,
    DSPICFG_MEM_L1P,
    DSPICFG_CACHE_SIZE_L1_MAX);
    /* Configure Cache size of L2 as 32K Cache. */
    retVal = DSPICFGCacheEnable(SOC_DSP_ICFG_BASE,
    DSPICFG_MEM_L2,
    DSPICFG_CACHE_SIZE_L2_32K); --> Set the size appropriate to your system.
    /* Make the initialized DDR regions cachable. The variables are such that
    * they fall in the same L2 Cache set. Since the L2 cache supports 4 ways
    * each variable access will cause all 4 ways to be populated for the same
    * set.
    */
    /* DO this for every 16 MB region your code would access */
    retVal = DSPICFGSetMAR(SOC_DSP_ICFG_BASE, (uint32_t)< Your 1st 16 MB starting address >,
    DSPICFG_MAR_PC);
    retVal = DSPICFGSetMAR(SOC_DSP_ICFG_BASE, (uint32_t)< Your 2nd 16 MB starting address >,
    DSPICFG_MAR_PC);

    ....


    retVal = DSPICFGSetMAR(SOC_DSP_ICFG_BASE, (uint32_t)< Your nth 16 MB starting address >,
    DSPICFG_MAR_PC);

    MMU settings or XMC settings would not get you the performance boost. They can be used for segregating memory regions and access permissions for usecases like FFI

    Thanks and Regards,
    Piyali
  • 0 in reply to Piyali Goswami
    TI__Guru 55685 points
    Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh