I have a 32bit Host Port Interface between a C6416T Big Endian (CPU) and Altera CycloneV SoC (host) running embedded linux. The Arm Cores of the SoC access the HPI via the SoC FPGA memory mapped interface.
There seems to be a 4 byte endian switch occurring on data transferred over the interface. i.e uint32 0xAABBCCDD in DSP memory comes out as uint32 0xAABBCCDD in the Arm host without a call to ntohl() or similar byte swapping function, in essence it seems an endian swap has occured across the bus. This is causing issues when writing structures containing uint16 or similar data.
A struct defined in the DSP as:
struct
{
uint16 A = 75;
uint16 B = 42;
}
Is coming over to the arm memory as
struct
{
uint16 A = 42;
uint16 B = 75;
}
We have to perform a 32bit byte swap to return the data to big endian, before using the ntohs() function to swap back to little endian on a 2 byte basis.
Is this expected behaviour for the HPI in 32 bit mode (that the data is endian swapped on a 4 byte alignment)? The only references I could find for endianess in the documentation were with regards to 16bit operation HWOB etc.
Due to legacy code support and shared code with C55x series chips it is not possible to run the DSP as little endian.
Thanks in advance