AM3351: DDR2 signal integrity AM3351 measurements fail

Francois Veger

Part Number: AM3351

Hi,

At the moment I'm working on a CPU board with custom DDR2 routing which we have implemented according to the datasheet (figure 7-39), one DDR2 device connected with 16 bit data bus width.

The DDR2 is functional and we are able to run firmware on it so it is stable, but when I measure the signals (with a MSO Tektronix scope and DDR2 analysis tools) I get a fail which I do not really understand.

The fail is about the Vswing(max) on CK(#) and DQS(#). in the JEDEC it is stated that is should be 1 Volt maximum but we use the DDR2 with 1V8 supply so we go over the requirement at least 0.5V and so the test is fail.

Is there any information/knowledge about this signal? The JEDEC does states it is a "test signal waveform", so do I need to enable test signals for DDR2 measurement?

Thank you for the support.

over 6 years ago

0 Tom Johnson 16214 over 6 years ago

TI__Mastermind 46460 points

Francois,

I have a few questions:

What is the bandwidth and sample rate of the scope when taking this measurement?
What is the bandwidth of the scope probe? Is it properly calibrated?
Are you making a differential measurement of CK and CK# (same for DQS and DQS#)?
If differential, are you using a differential probe or 2 single-ended probes?
Please provide the JEDEC spec number and version that you are referencing.

Tom

0 Francois Veger over 6 years ago in reply to Tom Johnson 16214

Prodigy 240 points

Hi Tom,

Thank you for the reply, here are my answers:

1. The bandwidth of the scope is 2 GHz and sample rate of the scope is set to 10 GS/s when taking the measurement.

2, The probe bandwidth is 1.5GHz

3/4. Yes I use 2 probes single ended. To measure the CK and CK#. (Similar with the DQS and DQS# but here I also measure the DQ to align on a write.)

5. I refer to the JESD79-2F (section 6, page 64)

François

0 Tom Johnson 16214 over 6 years ago in reply to Francois Veger

TI__Mastermind 46460 points

François,

Please post scope captures of CK and DQS.

Tom

0 Francois Veger over 6 years ago in reply to Tom Johnson 16214

Prodigy 240 points

Hi Tom,

Here you can find the measurement of the CK:

(Yellow -> CK; Blue -> CK#)

And the measurement of the DQS (Write):

Where Yellow-> DQS; Blue -> DQ7; purple -> DQS#.

0 JJD over 6 years ago in reply to Francois Veger

TI__Guru* 86040 points

Francois, it looks like you clock signal has the correct swing, but data is too high. Have you tried to adjust drive strength to see if that helps?

Regards,
James

0 Brad Griffis over 6 years ago in reply to JJD

TI__Guru*** 125430 points

Francois,

Please download the following diagnostic script:

git.ti.com/.../am335x-ddr-analysis.dss

It should be run after you DDR is fully configured. Directions on how to run it can be found here:

git.ti.com/.../README

Please attach the resulting *.txt file from your desktop here in this thread.

Best regards,
Brad

0 Francois Veger over 6 years ago in reply to Brad Griffis

Prodigy 240 points

Hi James, Brad.

Sorry for the delay on answering but I'm trying to get my XDS510; CCS8.3 and the AM335x working together. (It worked before on a Win7 laptop but I had to switch to a Win 10. But now it gives the error:
"Error connecting to the target:
Error 0x20000220/-1266
Severe Error during: Execution, OCS,
The target is held in RESET. This could be either due to wait-in-reset (WIR) or due to application induced reset."

@James: the CK/CK# is according to my measurement not okay as well, I'll check this again. For the DQS I have set my drive-strenght to low and ODT to 50E.
@Brad: I'll try to get the script running when JTAG works again.

0 Tom Johnson 16214 over 6 years ago in reply to Francois Veger

TI__Mastermind 46460 points

Francois,

I am not sure if this is a long-term solution but I have heard that the following may be needed to get CCS8 to behave on Windows 10:

This requires adding c:\ti\ccsv8\utils\cygwin\sh.exe” to Windows defender excluding list

Please see if this resolved the issue.

Tom

0 Francois Veger over 6 years ago in reply to Brad Griffis

Prodigy 240 points

Brad, Tom,

I have managed to get it running (on a Windows 7 PC, I was not able to get it running on a Windows 10 PC), although I'm not sure if it is running correctly. I get the following output:

Skipping read of EMIF registers since EMIF clock disabled.
* EMIF registers are not readable when in DS0 state
* If you are attempting to enter DS0 this is normal.

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x00000000
* ddr_ba2 Pullup/Pulldown disabled
* ddr_wen Pullup/Pulldown disabled
* ddr_ba0 Pullup/Pulldown disabled
* ddr_a5 Pullup/Pulldown disabled
* ddr_ck Pullup/Pulldown disabled
* ddr_ckn Pullup/Pulldown disabled
* ddr_a3 Pullup/Pulldown disabled
* ddr_a4 Pullup/Pulldown disabled
* ddr_a8 Pullup/Pulldown disabled
* ddr_a9 Pullup/Pulldown disabled
* ddr_a6 Pullup/Pulldown disabled
* Bits 9:5 control ddr_ck and ddr_ckn
- Slew fastest
- Drive Strength 5 mA
* Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_CMD1_IOCTRL = 0x00000000
* ddr_a15 Pullup/Pulldown disabled
* ddr_a2 Pullup/Pulldown disabled
* ddr_a12 Pullup/Pulldown disabled
* ddr_a7 Pullup/Pulldown disabled
* ddr_ba1 Pullup/Pulldown disabled
* ddr_a10 Pullup/Pulldown disabled
* ddr_a0 Pullup/Pulldown disabled
* ddr_a11 Pullup/Pulldown disabled
* ddr_casn Pullup/Pulldown disabled
* ddr_rasn Pullup/Pulldown disabled
* Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_CMD2_IOCTRL = 0x00000000
* ddr_cke Pullup/Pulldown disabled
* ddr_resetn Pullup/Pulldown disabled
* ddr_odt Pullup/Pulldown disabled
* ddr_a14 Pullup/Pulldown disabled
* ddr_a13 Pullup/Pulldown disabled
* ddr_csn0 Pullup/Pulldown disabled
* ddr_a1 Pullup/Pulldown disabled
* Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_DATA0_IOCTRL = 0x00000000
* ddr_d8 Pullup/Pulldown disabled
* ddr_d9 Pullup/Pulldown disabled
* ddr_d10 Pullup/Pulldown disabled
* ddr_d11 Pullup/Pulldown disabled
* ddr_d12 Pullup/Pulldown disabled
* ddr_d13 Pullup/Pulldown disabled
* ddr_d14 Pullup/Pulldown disabled
* ddr_d15 Pullup/Pulldown disabled
* ddr_dqm1 Pullup/Pulldown disabled
* ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs1, ddr_dqsn1
- Slew fastest
- Drive Strength 5 mA
* Bits 4:0 control ddr_d[15:8], ddr_dqm1
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_DATA1_IOCTRL = 0x00000000
* ddr_d0 Pullup/Pulldown disabled
* ddr_d1 Pullup/Pulldown disabled
* ddr_d2 Pullup/Pulldown disabled
* ddr_d3 Pullup/Pulldown disabled
* ddr_d4 Pullup/Pulldown disabled
* ddr_d5 Pullup/Pulldown disabled
* ddr_d6 Pullup/Pulldown disabled
* ddr_d7 Pullup/Pulldown disabled
* ddr_dqm0 Pullup/Pulldown disabled
* ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs0, ddr_dqsn0
- Slew fastest
- Drive Strength 5 mA
* Bits 4:0 control ddr_d[7:0], dqm0
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_IO_CTRL = 0x00000000
* Bit 31: DDR_RESETn controlled by EMIF.
* Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00000000
* VTP disabled (expected in DS0).
CONTROL: VREF_CTRL = 0x00000000
* VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000000
* CKE gated (forces pin low).

This result do I get when:
- SPL file is not loaded
- SPL file is loaded through (through x-modem interface)
- SPL file (through x-modem interface) and the u-boot image (through Y-modem interface) are loaded.

Additionally I can run a GEL file memory test which is passing (through JTAG). (Also I could not find the "In the Target Configurations window, right-click on your ccxml file and select "Launch Selected Configuration" so I just enabled debug mode, connect to the target and run the script.)

0 JJD over 6 years ago in reply to Francois Veger

TI__Guru* 86040 points

Francois, something went wrong when running the script. It should be run after the EMIF is configured. It looks like the script was run before the EMIF is configured (or maybe the EMIF failed to configure properly). Can you try booting to uboot, then running the script?

Regards,
James

0 Francois Veger over 6 years ago in reply to JJD

Prodigy 240 points

Hi James,

I think I did, when I load the SPL the DDR2 is initialized. (I have verified this when using the GEL file).

I connect the XDS510USB and power the board. I start debug session and connect UART to a "extra putty" window and enable x-modem to load the SPL. After this I give my board a power cycle so it loads the SPL through UART.

When the SPL is loaded I connect the Cortex-A8 CPU in CCS. The status is "Suspended". Then I load the GEL file and I'm able to run the "DDR_DataTransferCheck". This gives pass. (When I run this without SPL loaded it fails as expected.)

Now I run the "am335x-ddr-analysis.dss" script in the Scripting Console and it just gives output like before the output with EMIF disabled and such.(With or without the CPU connected).

I checked a bit in the code and it seems going wrong with the check "if (//original_CM_PER_L3_CLKSTCTRL & 1<<2) {". When I change it to "if(1){" it gives the following output:

EMIF: SDRAM_CONFIG = 0x43845732
* Bits 26:24 (reg_ddr_term) set for 50 Ohm (011b)
* Bits 19:18 (reg_sdram_drive) set for weak drive (01b)
EMIF: PWR_MGMT_CTRL = 0x00000000
* ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit
* Please see the silicon errata for more details.
DDR PHY: DDR_PHY_CTRL_1 = 0x00100306
* Bits 9:8 (reg_phy_rd_local_odt) configured as half thevenin termination

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000004
*(0x4c000008) = 0x43845732
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x2000040d
*(0x4c000014) = 0x0000040d
*(0x4c000018) = 0x0666a392
*(0x4c00001c) = 0x0666a392
*(0x4c000020) = 0x142431ca
*(0x4c000024) = 0x142431ca
*(0x4c000028) = 0x0000021f
*(0x4c00002c) = 0x0000021f
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffffff
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x0aac61c9
*(0x4c000084) = 0x0115a596
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0xf61fc0a5
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x00000000
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00100306
*(0x4c0000e8) = 0x00100306
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x00000000
* ddr_ba2 Pullup/Pulldown disabled
* ddr_wen Pullup/Pulldown disabled
* ddr_ba0 Pullup/Pulldown disabled
* ddr_a5 Pullup/Pulldown disabled
* ddr_ck Pullup/Pulldown disabled
* ddr_ckn Pullup/Pulldown disabled
* ddr_a3 Pullup/Pulldown disabled
* ddr_a4 Pullup/Pulldown disabled
* ddr_a8 Pullup/Pulldown disabled
* ddr_a9 Pullup/Pulldown disabled
* ddr_a6 Pullup/Pulldown disabled
* Bits 9:5 control ddr_ck and ddr_ckn
- Slew fastest
- Drive Strength 5 mA
* Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_CMD1_IOCTRL = 0x00000000
* ddr_a15 Pullup/Pulldown disabled
* ddr_a2 Pullup/Pulldown disabled
* ddr_a12 Pullup/Pulldown disabled
* ddr_a7 Pullup/Pulldown disabled
* ddr_ba1 Pullup/Pulldown disabled
* ddr_a10 Pullup/Pulldown disabled
* ddr_a0 Pullup/Pulldown disabled
* ddr_a11 Pullup/Pulldown disabled
* ddr_casn Pullup/Pulldown disabled
* ddr_rasn Pullup/Pulldown disabled
* Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_CMD2_IOCTRL = 0x00000000
* ddr_cke Pullup/Pulldown disabled
* ddr_resetn Pullup/Pulldown disabled
* ddr_odt Pullup/Pulldown disabled
* ddr_a14 Pullup/Pulldown disabled
* ddr_a13 Pullup/Pulldown disabled
* ddr_csn0 Pullup/Pulldown disabled
* ddr_a1 Pullup/Pulldown disabled
* Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_DATA0_IOCTRL = 0x00000000
* ddr_d8 Pullup/Pulldown disabled
* ddr_d9 Pullup/Pulldown disabled
* ddr_d10 Pullup/Pulldown disabled
* ddr_d11 Pullup/Pulldown disabled
* ddr_d12 Pullup/Pulldown disabled
* ddr_d13 Pullup/Pulldown disabled
* ddr_d14 Pullup/Pulldown disabled
* ddr_d15 Pullup/Pulldown disabled
* ddr_dqm1 Pullup/Pulldown disabled
* ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs1, ddr_dqsn1
- Slew fastest
- Drive Strength 5 mA
* Bits 4:0 control ddr_d[15:8], ddr_dqm1
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_DATA1_IOCTRL = 0x00000000
* ddr_d0 Pullup/Pulldown disabled
* ddr_d1 Pullup/Pulldown disabled
* ddr_d2 Pullup/Pulldown disabled
* ddr_d3 Pullup/Pulldown disabled
* ddr_d4 Pullup/Pulldown disabled
* ddr_d5 Pullup/Pulldown disabled
* ddr_d6 Pullup/Pulldown disabled
* ddr_d7 Pullup/Pulldown disabled
* ddr_dqm0 Pullup/Pulldown disabled
* ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs0, ddr_dqsn0
- Slew fastest
- Drive Strength 5 mA
* Bits 4:0 control ddr_d[7:0], dqm0
- Slew fastest
- Drive Strength 5 mA
CONTROL: DDR_IO_CTRL = 0x00000000
* Bit 31: DDR_RESETn controlled by EMIF.
* Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00000000
* VTP disabled (expected in DS0).
CONTROL: VREF_CTRL = 0x00000000
* VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000000
* CKE gated (forces pin low).

0 JJD over 6 years ago in reply to Francois Veger

TI__Guru* 86040 points

Francois, I'm sorry but there still seems to be something wrong with the script. I have checked on my EVM and see similar issues. Please try with the .dss attached while i try to fix it in the git tree.

The drive strength and ODT that you reported is what is set in the DDR. What I'm looking for is what you set in the EMIF controller, which is described in the IOCTRL registers (that so far, are reading zeros because of the bug in the dss script). Once you run the new script, we should be able to see what you have set in the EMIF controller.

Regards,

James

am335x-ddr-analysis.zip

0 Francois Veger over 6 years ago in reply to JJD

Prodigy 240 points

Hi James,

I have ran the updated script again with the following output:

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000004
*(0x4c000008) = 0x43845732
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x2000040d
*(0x4c000014) = 0x0000040d
*(0x4c000018) = 0x0666a392
*(0x4c00001c) = 0x0666a392
*(0x4c000020) = 0x142431ca
*(0x4c000024) = 0x142431ca
*(0x4c000028) = 0x0000021f
*(0x4c00002c) = 0x0000021f
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffffff
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x0aab60c8
*(0x4c000084) = 0x011845c6
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0xa4dfd2f5
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x00000000
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00100306
*(0x4c0000e8) = 0x00100306
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x00000373
* ddr_ba2 Pullup/Pulldown disabled
* ddr_wen Pullup/Pulldown disabled
* ddr_ba0 Pullup/Pulldown disabled
* ddr_a5 Pullup/Pulldown disabled
* ddr_ck Pullup/Pulldown disabled
* ddr_ckn Pullup/Pulldown disabled
* ddr_a3 Pullup/Pulldown disabled
* ddr_a4 Pullup/Pulldown disabled
* ddr_a8 Pullup/Pulldown disabled
* ddr_a9 Pullup/Pulldown disabled
* ddr_a6 Pullup/Pulldown disabled
* Bits 9:5 control ddr_ck and ddr_ckn
- Slew slowest
- Drive Strength 8 mA
* Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
- Slew fast
- Drive Strength 8 mA
CONTROL: DDR_CMD1_IOCTRL = 0x00000373
* ddr_a15 Pullup/Pulldown disabled
* ddr_a2 Pullup/Pulldown disabled
* ddr_a12 Pullup/Pulldown disabled
* ddr_a7 Pullup/Pulldown disabled
* ddr_ba1 Pullup/Pulldown disabled
* ddr_a10 Pullup/Pulldown disabled
* ddr_a0 Pullup/Pulldown disabled
* ddr_a11 Pullup/Pulldown disabled
* ddr_casn Pullup/Pulldown disabled
* ddr_rasn Pullup/Pulldown disabled
* Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
- Slew fast
- Drive Strength 8 mA
CONTROL: DDR_CMD2_IOCTRL = 0x00000373
* ddr_cke Pullup/Pulldown disabled
* ddr_resetn Pullup/Pulldown disabled
* ddr_odt Pullup/Pulldown disabled
* ddr_a14 Pullup/Pulldown disabled
* ddr_a13 Pullup/Pulldown disabled
* ddr_csn0 Pullup/Pulldown disabled
* ddr_a1 Pullup/Pulldown disabled
* Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
- Slew fast
- Drive Strength 8 mA
CONTROL: DDR_DATA0_IOCTRL = 0x00000373
* ddr_d8 Pullup/Pulldown disabled
* ddr_d9 Pullup/Pulldown disabled
* ddr_d10 Pullup/Pulldown disabled
* ddr_d11 Pullup/Pulldown disabled
* ddr_d12 Pullup/Pulldown disabled
* ddr_d13 Pullup/Pulldown disabled
* ddr_d14 Pullup/Pulldown disabled
* ddr_d15 Pullup/Pulldown disabled
* ddr_dqm1 Pullup/Pulldown disabled
* ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs1, ddr_dqsn1
- Slew slowest
- Drive Strength 8 mA
* Bits 4:0 control ddr_d[15:8], ddr_dqm1
- Slew fast
- Drive Strength 8 mA
CONTROL: DDR_DATA1_IOCTRL = 0x00000373
* ddr_d0 Pullup/Pulldown disabled
* ddr_d1 Pullup/Pulldown disabled
* ddr_d2 Pullup/Pulldown disabled
* ddr_d3 Pullup/Pulldown disabled
* ddr_d4 Pullup/Pulldown disabled
* ddr_d5 Pullup/Pulldown disabled
* ddr_d6 Pullup/Pulldown disabled
* ddr_d7 Pullup/Pulldown disabled
* ddr_dqm0 Pullup/Pulldown disabled
* ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs0, ddr_dqsn0
- Slew slowest
- Drive Strength 8 mA
* Bits 4:0 control ddr_d[7:0], dqm0
- Slew fast
- Drive Strength 8 mA
CONTROL: DDR_IO_CTRL = 0x00000000
* Bit 31: DDR_RESETn controlled by EMIF.
* Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00010167
* VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
* VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000001
* CKE controlled by EMIF (normal/ungated operation).

0 JJD over 6 years ago in reply to Francois Veger

TI__Guru* 86040 points

Francois,
great! Finally you got a good output. Can you try changing all of the DDR_DATAx_IOCTRL registers to 0x18B.

Thanks,
James

Processors

Processors forum

AM3351: DDR2 signal integrity AM3351 measurements fail