Tool/software: Linux
Hello,
I'm looking for a guide on how to configure a build of TI SDK Linux for AM57xx,
to provide a PCIe Root Complex functionality.
We are using the TI Arago project 5.2.0.10, running bitbake to build arago-base-tisdk-image (respective the arago-core-tisdk-image).
We would like to implement PCIe x1 endpoint (EP) inside FPGA, which would connect directly to AM57xx.
No other PCIe devices are to be connected.
The FPGA will run our custom HDL code, and we would like to provide a bidirectional channel / interrupt system,
to transfer messages between AM57xx Linux user-space application, via PCIe, to FPGA, and vice-versa.
1] Are there any specific HW related requirements (f.ex. clock lane routing), that we shall follow ?
We'd like to connect Sitara to a bigger Xilinx FPGA.
2] I do assume it is based on a custom TI Kernel Driver, within the TI Processor SDK Linux.
Do we need to reconfigure it, or is it by default included in the base/core image (recipe) ?
3] Also, is there a user-space example application, which would show how to talk to our EP via the PCIe RC TI Kernel Driver ?
We would need this as well.
I'm browsing the TI Wiki and E2E forum, but it seems the information is split through many places.
Not sure which is actual and what not.
Could you point me to a proper link (wiki etc) ?
That would be very appreciated.
thanks,
a.
