Part Number: AM3354
Dears,
We use TI's AM3354,have below design question,need help to advice:
1.we want to achieve functional,we use GPMC read data from FPGA, addressable space is in CSn2 and CSn3,addressable range is 4096 address space(12 address line with each have 16 bit word),the interrupt interval is 10ms,each time read 4096 data.
when AM3354 receive GPIO1_8 's interrupt request，should serial read CSn2 addressing space data (4096).
when AM3354 receive GPIO1_9 's interrupt request，should serial read CSn3 addressing space data ,cycle read all the time.
all interrupt active on rising edge.
How to write it's GPMC driver,and how to remapping Pins and how to set Interrupt?
2.We use AM3354's RGMII to get GB ethernet, the PHY IC is AR8031, have polarity self-correction function,does this function need open in software?
3.We use AM3354's SPI extend two PCS W5500 ICs,these two channel W5500 ICs take share MISO, MOSI and SPI-CLK,only the enable signal is independent,how to write W5500's driver?
(W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that provides easier Internet connection to embedded systems)
Thanks!
