AMIC120: Accessing shared memory from PRU-ICSS and A9

Hello,

Does shared memory in PRU-ICSS have any hardware to prevent access collision (accessing at the same time from A9 and PRU core and reading wrong data)?
If yes, could you tell me what it is or any URL described about it?
If no, could you tell me how to prevent access collision in shared memory?

Regards,

U-SK