AM6548: Use of MSMC SRAM in TI-RTOS application

Dominic,

From an architecture stand point. For best performance of application from R5F, we typically recommend users to leverage OCRAM and R5F TCM memory since it exists in the MCU domain but the SDK uses MSMC because not all applications can fit in the available 256 KB of OCRAM memory and so MSMC.

Having said that let me explain the reserved memory in the MSMC. As you know on this device architecture, DMSC/Cortex M3 is the power management and resource management master core and the other cores setup proxy channels using navigator subsystem for messaging with the M3. The region reserved in memory is for these secure proxy structure definition that are used for messaging with SYSFW running on the M3. The MSMC_NOCACHE is used to configure the cache for buffers backing this secure proxy and ring memory. You can find the reference to this MSMC usage in the TISCI USer guide for the SYSFW here:

We planned to add this as a in integration usage note but It looks like the integration document notes are waiting to be merged with Processor SDK RTOS documentation. Here is a preview of the documentation:

Configuration of R5F cache shouldn`t impact this last 56KB region. If you are application also uses A53 to send messages to M3 then using this region can impact the system/.  In the longer term, we plan you add an API so cores can query the MSMC usage and also move the MSMC_DMSC region to the end of the MSMC region so it is not in the middle of the MSMC range. 

Let me check on the MSMC usage in the USB driver and the board configuration and get back to you but I suspect that since the MSMC is used by A53 applications to talk to DMSC, the R5F developers don`t consider it to be reserved. 

Regards,

Rahul 

Dominic,

The MSMC along with the two dual A53  clusters forms the compute cluster on the AM65x device. The MSMC can be configured as SRAM as is the current implementation or can be configured as L3 cache for external EMIF memory access from the A53.   The MSMC_CACHE_CTRL allows you to configure the MSMC SRAM as L3 cache.  This feature essentially  allows AM65x device to support two cache hierarchies :

1. Shared L3 SRAM mode (L1 and L2 cache MSMC SRAM)      <---- Default

2. Shared L3 cache mode (L1 and L2 and MSMC L3 cache DDR)  

You can also support a third hybrid hierarchy by configure MSMC as part cache and part SRAM.  If you set 1 MB of MSMC as L3 cache then you can use the rest as SRAM.

An example use cases  would be the  configuration of quad A53  in SMP mode, the MSMC forms the shared cache that allows for synchronization across four cores that are implemented across two clusters on the chip.  typically if you see devices like AM572x (dual core A15 device) or K2H (quad core A15 device), they have a shared L2 that provide shared cache for the SMP mode implementation since they are all implemented using a single cluster.

An example function to setup MSMC Cache using CSL code would be as follows:

// Following values are for SOC_AM6X (Maxwell)
// Valid Maxwell cache sizes (per MSMC3 spec):
// 0.25MB, 0.5MB, 0.75MB, 1MB, 1.25MB, 1.5MB, 1.75MB, 2MB
    #define     MSMC_L3MAX          0x200000        // 2.0  MB
    #define     MSMC_L3MIN           0x40000        // 0.25 MB
    #define     MSMC_SRAM_BANKS             2
    #define     MSMC_SRAM_GROUPWAYS         4
    #define     MSMC_SRAM_DATAPATH         32
    #define     MSMC_SRAM_CACHELINE        64
    #define     MSMC_SRAM_ENTRIES         512


// The following defines are used here until msmc CSLR is available in git repo
#define CSL_MSMC_CFGS0_REGS_BASE                                        (0x0E000000U)
#define CSL_MSMC_CFGS0_CACHE_CTRL                                       (0x00001000U)
#define CSL_MSMC_CFGS0_CACHE_CTRL_CACHE_SIZE_MASK                       (0x000000000000000FU)
#define CSL_MSMC_CFGS0_CACHE_STAT_SZ_TRANSITION_MASK                    (0x0000000000000010U)
#define MSMCCFG     (CSL_COMPUTE_CLUSTER0_MSMC_CFGS0_BASE)



/* Set MSMC SRAM as L3 cache based on size in bytes
* Usage notes:
*     This API is for setting L3 cache from non-cache (size = 0) only
*     Less than MSMC_L3MIN returns ERROR even though size of 0 is a valid size
*     Actual cache size will be the valid minimum of value passed to function
*     Example: 310KB will result in 256KB cache size
* Input: desired L3 size (has to be permissible for selected SoC)
* Return: 0 == error
*/         final cache size in bytes

uint32_t msmcSetL3CacheSize(uint32_t size)
{
    uint32_t status;
    uint32_t    val = 0;
    volatile uint64_t *cacheCtrl_ptr = (uint64_t *) (MSMCCFG + CSL_MSMC_CFGS0_CACHE_CTRL);
    // Test desired cache size for valid sizes
    // If CACHE_CTRL.CACHESIZE[3-0] is non-zero, or size is out of range, return ERROR
    if (/* (*cacheCtrl_ptr & CSL_MSMC_CFGS0_CACHE_CTRL_CACHE_SIZE_MASK) || */ ((size < MSMC_L3MIN) || (size > MSMC_L3MAX)))
        status = 0;
    else
    {
        // Calculate "Group-Ways" value for CACHE_CTRL.CACHE_SIZE
        val = (size >> 16) / MSMC_SRAM_GROUPWAYS;
        // Write cache size
        *cacheCtrl_ptr = (*cacheCtrl_ptr & !CSL_MSMC_CFGS0_CACHE_CTRL_CACHE_SIZE_MASK) + val;
        // Wait for transition to complete
        while ( *cacheCtrl_ptr & CSL_MSMC_CFGS0_CACHE_STAT_SZ_TRANSITION_MASK)
            ;
        // Verify again
        if ((*cacheCtrl_ptr & CSL_MSMC_CFGS0_CACHE_CTRL_CACHE_SIZE_MASK) == val)
           status =  val * MSMC_SRAM_GROUPWAYS << 16;    // return actual size used for L3 cache
        else   {
            status = 0;    // this should not happen so flag as ERROR
        }
    }
    return status;
}

Hope this helps.

Regards,

Rahul