RTOS/TDA2PXEVM: How to assign MCSPI4 IRQ to IPU??

Wooyeop Kim

Intellectual 430 points

Part Number: TDA2PXEVM

Tool/software: TI-RTOS

Dear TI

How to assign MCSPI4 IRQ to IPU??

Hi, I `m developing MCSPI on TDA2PX.

We are using MCSPI4 (McSPI Instance 3)

But, we can not get IRQ about MCSPI4 (CSL_INTC_EVENTID_MCSPIINT3) on IPU processor.

I found some informaiotn in TDA2PX TRM that MCSPI1_IRQ and MCSPI2_IRQ are assigned.

I want that MCSPI4 is assigned to IPU.

Please help me ~~!

Thank you.

over 6 years ago

0 Rishabh Garg over 6 years ago

TI__Guru 55685 points

Hi,

You should use CSL_XBAR_MCSPI4_IRQ for connecting MCSPI4 interrupts to IPU as defined in PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\csl\soc\tda2px\csl_device_xbar.h.
To see how IRQ crossbar can be connected please refer to EDMA example, PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\csl\example\edma\edma_test\main.c.

Regards,
Rishabh

0 Wooyeop Kim over 6 years ago in reply to Rishabh Garg

Intellectual 430 points

Hi

I trid to connected IRQ crossbar as you mentioned.
but, during init, system hang up..... as below

[IPU1-1] 17.250015 s: ***** IPU1_1 Firmware build time 16:07:59 Mar 25 2019
[IPU1-1] 17.250167 s: *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU1-1] 17.311687 s: SYSTEM: Notify register to [IPU1-0] line 0, event 15...
[IPU1-1] 17.311901 s: SYSTEM: Notify register to [IPU2] line 0, event 15...
[IPU1-1] 17.312023 s: SYSTEM: Notify register to [DSP1] line 0, event 15...
[IPU1-1] 17.312145 s: SYSTEM: Notify register to [DSP2] line 0, event 15...
[IPU1-1] 17.312267 s: SYSTEM: Notify register to [EVE1] line 0, event 15...
[IPU1-1] 17.312389 s: SYSTEM: Notify register to [EVE2] line 0, event 15...
[IPU1-1] 17.312480 s: SYSTEM: Notify register to [HOST] line 0, event 15...
[IPU1-1] 17.314341 s: SYSTEM: System Common Init in progress !!!
[IPU1-1] 17.315317 s: UTILS: CIO: Init Done !!!
[IPU1-1] 17.315439 s: SYSTEM: IPC init in progress !!!
[IPU1-1] 17.315531 s: SYSTEM: Notify init done !!!
[IPU1-1] 17.317178 s: SYSTEM: MsgQ init done !!!
[IPU1-1] 17.317910 s: SYSTEM: Work Queue init done !!!
[IPU1-1] 17.317971 s: SYSTEM: IPC init DONE !!!
[IPU1-1] 17.321539 s: SYSTEM: Initializing TIOVX ...
[IPU1-1] 17.321722 s: VX_ZONE_INIT:Enabled
[IPU1-1] 17.321844 s: VX_ZONE_ERROR:Enabled
[IPU1-1] 17.321966 s: VX_ZONE_WARNING:Enabled
[IPU1-1] 17.325901 s: VX_ZONE_INIT:[tivxInit:52] Initialization Done !!!
[IPU1-1] 17.326023 s: SYSTEM: Initializing TIOVX ... Done !!!
[IPU1-1] 17.326084 s: SYSTEM: System Common Init Done !!!
[IPU1-1] 17.326206 s: SYSTEM: System IPU1_1 Init in progress !!!
[IPU1-1] 17.326267 s: wooyeop : Utils_dmaInit()
[IPU1-1] 17.327060 s: UTILS: DMA: HWI Create for INT25 !!!
[IPU1-1] 17.327273 s: UTILS: DMA: Utils_dmaInit() for instance 0 (0)
[IPU1-1] 17.327365 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024
[IPU1-1] 17.327548 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 655360 B (640 KB), Free size = 647560 B (632 KB)
[IPU1-1] 17.327731 s: SYSTEM: Initializing Links !!!
[IPU1-1] 17.433050 s: UTILS: PRF: ##### Cannot allocate Object for SYNC1 ####
[IPU1-1] 17.436039 s: UTILS: PRF: ##### Cannot allocate Object for SYNC2 ####
[IPU1-1] 17.438784 s: UTILS: PRF: ##### Cannot allocate Object for SYNC3 ####
[IPU1-1] 17.441712 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM0 ####
[IPU1-1] 17.444946 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM1 ####
[IPU1-1] 17.447813 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM2 ####
[IPU1-1] 17.450863 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM3 ####
[IPU1-1] 17.454187 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM4 ####
[IPU1-1] 17.457115 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM5 ####
[IPU1-1] 17.460379 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM6 ####
[IPU1-1] 17.463582 s: UTILS: PRF: ##### Cannot allocate Object for ALGORITHM7 ####
[IPU1-1] 17.463704 s: SYSTEM: Initializing Links ... DONE !!!
[IPU1-1] 17.463795 s: SYSTEM: System IPU1_1 Init Done !!!
[HOST ] 17.304062 s: ***** A15_0 Firmware build time 16:07:23 Mar 25 2019
[HOST ] 17.304093 s: *** SYSTEM: CPU Frequency <ORG = 750000000 Hz>, <NEW = 750000000 Hz>
[HOST ] 17.310406 s: SYSTEM: Notify register to [IPU1-0] line 0, event 15...
[HOST ] 17.310437 s: SYSTEM: Notify register to [IPU1-1] line 0, event 15...
[HOST ] 17.310437 s: SYSTEM: Notify register to [IPU2] line 0, event 15...
[HOST ] 17.310467 s: SYSTEM: Notify register to [DSP1] line 0, event 15...
[HOST ] 17.310467 s: SYSTEM: Notify register to [DSP2] line 0, event 15...
[HOST ] 17.310498 s: SYSTEM: Notify register to [EVE1] line 0, event 15...
[HOST ] 17.310498 s: SYSTEM: Notify register to [EVE2] line 0, event 15...
[HOST ] 17.313121 s: SYSTEM: System Common Init in progress !!!
[HOST ] 17.313151 s: SYSTEM: IPC init in progress !!!
[HOST ] 17.313151 s: SYSTEM: Notify init done !!!
[HOST ] 17.313182 s: SYSTEM: MsgQ init done !!!
[HOST ] 17.313212 s: SYSTEM: Work Queue init done !!!
[HOST ] 17.313243 s: SYSTEM: IPC init DONE !!!
[HOST ] 17.313792 s: SYSTEM: Initializing TIOVX ...

I call CSL_xbarIrqConfigure on IPU1 side (Chains_common_vision.c ) as below

- CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_IPU1, CSL_XBAR_INST_IPU1_IRQ_31, CSL_XBAR_MCSPI4_IRQ);

I hardly modified offset in
- offset = CTRL_CORE_IPU1_IRQ_31_32( 0x50U)

Please check my work~~~!!

0 Rishabh Garg over 6 years ago in reply to Wooyeop Kim

TI__Guru 55685 points

Hi,

In case of Vision SDK, you should call BSP OSAL API BspOsal_irqXbarConnect().
Can you try if the same works for you.

Regards,
Rishabh

0 Wooyeop Kim over 6 years ago in reply to Rishabh Garg

Intellectual 430 points

I try to use BspOsal_irqXbarConnect() as you mention.
But, system hang is same...

After BspOsal_irqXbarConnect, what any other work I should add?

Thank you.

0 Rishabh Garg over 6 years ago in reply to Wooyeop Kim

TI__Guru 55685 points

Hi,

Where have you made the below mentioned change?
"I hardly modified offset in
- offset = CTRL_CORE_IPU1_IRQ_31_32( 0x50U)"

Regards,
Rishabh

0 Wooyeop Kim over 6 years ago in reply to Rishabh Garg

Intellectual 430 points

I made it in CSL_xbarDmaConfigure() of below path.
- Csl_device_xbar.c (ti_components\drivers\pdk_01_10_02_07\packages\ti\csl\soc\common)

++ offset = CTRL_CORE_IPU1_IRQ_31_32;

if ((0 == retVal) && (xbarIrq < CSL_IRQ_XBAR_MAX_COUNT))
{
/* MMR2 unlock */
#if defined (SOC_TDA3XX) || defined (SOC_DRA78x)
HW_WR_REG32(
SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE + CTRL_CORE_MMR_LOCK_2,
CTRL_CORE_MMR_LOCK_2_TOUNLOCK);
#else
HW_WR_REG32(
SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE + CTRL_CORE_MMR_LOCK_2,
CTRL_CORE_MMR_LOCK_2_MMR_LOCK_2_TOUNLOCK);
#endif

offset += (regIdx * 4U);
regVal = HW_RD_REG32(baseAddr + offset);
regVal &= ~mask;
regVal |= (xbarIrq << shift);
HW_WR_REG32(baseAddr + offset, regVal);

/* MMR2 lock */
#if defined (SOC_TDA3XX) || defined (SOC_DRA78x)
HW_WR_REG32(
SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE + CTRL_CORE_MMR_LOCK_2,
CTRL_CORE_MMR_LOCK_2_TOLOCK);
#else
HW_WR_REG32(
SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE + CTRL_CORE_MMR_LOCK_2,
CTRL_CORE_MMR_LOCK_2_MMR_LOCK_2_TOLOCK);
#endif
}

Thank you.

0 Wooyeop Kim over 6 years ago in reply to Wooyeop Kim

Intellectual 430 points

Hi Rishabh~!

If I made BspOsal_irqXbarConnect(CSL_XBAR_INST_IPU1_IRQ_31, CSL_XBAR_MCSPI4_IRQ) or CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_IPU1, CSL_XBAR_INST_IPU1_IRQ_31, CSL_XBAR_MCSPI4_IRQ),
system is hang..regardless of offset.

Thank you!

0 Rishabh Garg over 6 years ago in reply to Wooyeop Kim

TI__Guru 55685 points

Hi Kim,

Can you try using some other interrupt line, maybe 31 is used by someone else in the system.
You can read back the register CTRL_CORE_IPU1_IRQ_31_32 before calling BspOsal_irqXbarConnect to confirm this.
Also you should use osal and not CSL.

Regards,
Rishabh

0 Wooyeop Kim over 6 years ago in reply to Rishabh Garg

Intellectual 430 points

Dear Rishabh

Before BspOsal_irqXbarConnect, CTRL_CORE_IPU1_IRQ_31_32 value is below
- HW_RD_REG32 val = b00082

Thank you

0 Prasad Konnur over 6 years ago in reply to Wooyeop Kim

TI__Expert 6065 points

Hi Kim,

The macro CSL_INTC_EVENTID_MCSPIINT3 is used inside the driver to register the interrupt.
This is defined in "<pdk_install_dir>/pdk/packages/ti/csl/soc/tda2px/cslr_soc_defines.h"
For TDA2Px the interrupt number 45 is used.
So you need to configure the crossbar to map the mcspi interrupt to IPU interrupt number 45.

Regards,
Prasad

0 Rishabh Garg over 6 years ago in reply to Prasad Konnur

TI__Guru 55685 points

Hi Kim,

It seems that MCSPI driver hard codes the interrupt number.
Can you please try Prasad's suggestion and let us know if the issue is resolved for you.

Regards,
Rishabh

0 Wooyeop Kim over 6 years ago in reply to Prasad Konnur

Intellectual 430 points

Hi Prasad

I try below
- BspOsal_irqXbarConnect(CSL_XBAR_INST_IPU1_IRQ_60, 45)

System hang is clear

But, I have another problem.
In driver, mcspiRegisterIntrHandler is called and int num is 45 in this function
but, interrupt handler (mcspiIntrHandler) is not called ..

What anything should I check for getting intterrupt.

Please help me~~ ASAP

Thank you

0 Wooyeop Kim over 6 years ago in reply to Wooyeop Kim

Intellectual 430 points

Hi ~!

I am working MCSPI4 as slave mode using MCSPI_OPMODE_INTERRUPT.
As I see example code, MCSPI_OPMODE_DMAINTERRUPT is used.

Is not MCSPI_OPMODE_INTERRUPT available?
And,
what does hwiNumber of Mcspi_Params mean? (please let me know how to set this vlaue)

Thank you.

0 Wooyeop Kim over 6 years ago in reply to Wooyeop Kim

Intellectual 430 points

HI TI~

Prease help me~
This is our emergency issue~~!

Thank you

0 Prasad Konnur over 6 years ago in reply to Wooyeop Kim

TI__Expert 6065 points

Hi Kim,

If you are using the slave mode then you need to use the MCSPI_OPMODE_INTERRUPT itself.
The ISR registered for the slave is mcspiSlaveIntrHandler.
Check if this is called?

Also in case of slave the external master will generate the clock only then hte transfer happens.
Check if the McSPI clock is generated by SPI master.
Can you probe the clock line if this is toggling?

Regards,
Prasad

0 Wooyeop Kim over 6 years ago in reply to Prasad Konnur

Intellectual 430 points

Hi ~

mcspiSlaveIntrHandler is not called.
Our SPI worked well in linux.
But, we changed os to rtos and then, we are facing Interrrupt problem now.
I will check SPI master clock and inform it you.

MCSPI4 is mapped to CROOSSBAR 43 in "Mapping of Device Interrupts to IRQ_CROSSBAR" in TRM.
But, it seems that there is not MCSPI4 input index(43) in "Interrupt Requests to IPU1_Cx_INTC " in TRM.

So, we tried to work to map CSL_XBAR_MCSPI4_IRQ(43) to CSL_XBAR_INST_IPU1_IRQ_60(reserve) as same below.
- BspOsal_irqXbarConnect(CSL_XBAR_INST_IPU1_IRQ_60, CSL_XBAR_MCSPI4_IRQ) --> mcspiSlaveIntrHandler is not called.
Also, we tried to work below list.
- BspOsal_irqXbarConnect(CSL_XBAR_INST_IPU1_IRQ_45, CSL_XBAR_MCSPI4_IRQ) --> system hang.

Please help me ~~!!!

0 Prasad Konnur over 6 years ago in reply to Wooyeop Kim

TI__Expert 6065 points

Hi Kim,

From the TRM below are the values you need to use for your use case.

int_source_no = 43 (Corresponding to McSPI4)

IPU_interrupt_no = 45 (IPU interrupt no, Used in driver)
XBAR_instance_no = 23 (xbar inst no Corresponding to IPU interrupt no 45)

You can use the BspOsal_irqXbarConnect(23, 43). This takes the xbar instance no and int Source.
Or alternatively use BspOsal_irqXbarConnectIrq(45, 43). This takes the cpu interrupt no and int Source.

Regards,
Prasad

0 Wooyeop Kim over 6 years ago in reply to Prasad Konnur

Intellectual 430 points

Hi

I tried BspOsal_irqXbarConnect(23, 43) --> it is same to BspOsal_irqXbarConnect(CSL_XBAR_INST_IPU1_IRQ_45, CSL_XBAR_MCSPI4_IRQ)
But, this work to cause system hang.....

Also,I tried to use BspOsal_irqXbarConnectIrq(45, 43), but it is same...

And,

When I chked SPI pins with oiur HW team, Clock, MOSI, MISO line is no problem.

Beacuse of company security, I can not upload it.

Thank you

0 Prasad Konnur over 6 years ago in reply to Wooyeop Kim

TI__Expert 6065 points

Hi,

Can you share the McSPI register dump?
For McSPI4 instance from reg addr 0x480BA100 to 0x480BA1A0?

Are you running from IPU1 or IPU2?

Also share the crossbar reg value
CTRL_CORE_IPU1_IRQ_45_46 (0x4A00280C) - If running on IPU1,
CTRL_CORE_IPU2_IRQ_45_46 (0x4A002880) - If running on IPU2.

After the McSPI4 is configured, can you probe the McSPI lines (the CS and clk lines) and let us know if the clocks are toggeling?
From the master side what is the data read?
Do you get at least the first word passed to the slave driver in outBuffer of GIO_issue call, at the master side?

One more possible issue could be pin muxing.
Can you check to which pins of the SoC, the McSPI pins are connected on your board?
and check if the corresponding pin mux is done properly.
pinmux registers are present from 0x4A003400, check the corresponding pins are share the reg values.

Regards,
Prasad

0 Wooyeop Kim over 6 years ago in reply to Prasad Konnur

Intellectual 430 points

Dear Prasad

I cleared this issue.
Now, I can read some data from master and our master is other device.
But, I am facing other problem.

About it, I will open new case.

Thank you~

0 Prasad Konnur over 6 years ago in reply to Wooyeop Kim

TI__Expert 6065 points

Hi Kim,

Thanks for confirming the issue is resolved.

Can you post the fix that you did, may be it would be useful for others facing similar issue.

Also mark the answer that resolved your query by clicking the "This resolved my issue" button.
I will close this thread.

Regards,
Prasad

0 Wooyeop Kim over 6 years ago in reply to Prasad Konnur

Intellectual 430 points

Hi ~

Crossbar API works well~

I used printf in "mcspiSlaveIntrHandler" to check interrupt and it cause system hang...

When I remove it, system boot well~

Thank you.

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RTOS/TDA2PXEVM: How to assign MCSPI4 IRQ to IPU??