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TMS320C6678: Hyperlink Auto detect and set SerDes polarity .

LI XIANG
Intellectual 445 points
Part Number: TMS320C6678

Hi,

Here I got a problem when I enable Hyperlink, Mostly the Hyperlink can be enabled without error, but there is chance(about 1/150~200), it will find the following error status:

DSP1 hyperlink FAIL with link Status FDF00CF3, and ECC status: 0.
DSP2 hyperlink FAIL with link Status CCF0BDFB, and ECC status: 0.

While the correct status is:

DSP1 hyperlink successful with link Status FDF0BDFB, and ECC status: 0.
DSP2 hyperlink successful with link Status FDF0BDFB, and ECC status: 0.

As we can see, the error is due to the SerDes Lane plarity error which cause the link fail.

Since the Polarity is auto detect and set by Hyperlink module, may I know how can I handle the problem Or if there is an manual mode to set the polarity or not?

Thanks a lot.

B.R.

Jason

  • 0
    TI__Guru* 95265 points
    Hi,

    Please clarify:
    1. what software (MCSDK or Processor SDK RTOS) used for this? And what version?
    2. Is this TI 6678 EVM or your own board?
    3. What is Hyperlink speed? 6.25Gbps? 10Gbps? or other speed? x4 lanes correct?
    4. How the C6678 physically connected via Hyperlink port? cable? Is that reliable? Do you have any polarity reversal in connection (why the working case FDF0BDFB showing 3 lanes polarity reversal)? And if lane 0, 1,2, 3 connected to the lane 0, 1,2,3 on the other side in the order?
    5. The error happens at re-boot time or during run time?
    6. If it is run time, do you have to introduce heavy traffic to see this error? E.g, using EDMA to move data? Or using CPU to move data?
    7. If it is boot time, Hyperlink user guide 3.2.15 Lane Power Management Control Register (Base Address + 0x44), can you make sure quadlane is set, and singlelane is cleared, and zerolane is cleared?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 445 points

    Hi Eric,

    Thanks for your rapidly reply.

    Following is what you may concern:

    1. It's a Custom board, with 2 DSP, and the Hyperlink is to conenct the 2 DSP.(c6678) and we are running custom Bitstream on the both 2 DSP.(not RTOS)

    2. The Hyperlink speed is 3.125/Lane and total 4 lanes enabled.

    3. Actually only the lane 2(counter from 0) was inverted p and n at PCB board. and the Lane is 0->0 and 3->3. (As you can see the auto detect is inverting 0,1,3, and it works)

    4. The Error only happend when we boot-up DSP. no such issue for linkup over 5 days. After this problem happend, we can stop->reset->enable to recover.(base address + 0x58)

    5. for the PMCR(base Addr+0x44), I will try to review the code but actually this part cfg is reuse the C6678 Hyperlink sample code (K1_STK_v1.1). As you can see, the problem is not occured every time.

    So It's suspected may not relate to CFG. Anyway, just Guess, and I will check the CFG further.

    Thanks again.

  • 0 in reply to LI XIANG
    TI__Guru* 95265 points
    Hi,

    Thanks for the info! I knew there are instabilities for the boot test, whether you can get 100% reliability with hundreds of thousands time of reboot.

    We have another customer with Hyperlink 6.25Gbps x4 connection between KS II and KS I device, they have the similar issue. That board has 12 Hyperlink connections so we can easily do a reboot of 1000 times (to check 12,000 hyperlink connection). The solution is to do a reset when the driver detected the link status is not good after boot-up (as what you did in answer 4).

    Something may improve the stability:
    1. Check the register offset 0x44, just enable the quadlane mode, DON'T enable singlelane or zerolane mode (those are for power saving). There may be stability issue when transit from power saving to full power.
    2. In the MCSDK or PRSDK Hyperlink code, there is a function called hyplnkExampleEQAnalysis(). It will give you some indication:
    /*****************************************************************************
    * These functions performe equalization analysis on each lane.
    *
    * This will analyze the precursor (TX_TWPRE) and postcursor (TX_TWPST1) as
    * seen by the receiver on this side of the connection. For each lane and
    * each coefficient, it will print out whether the coefficient is too large
    * and/or too small.
    *
    * The analysis can be run several times with the same configuration in
    * order to decide if the configuration is optimal. When adjusting the
    * coefficients, remember that the transmitter (other device) is being
    * analyzed by this device.
    *
    * The result will be 4 ordered pairs, one ordered pair per lane.
    * The first digit in the pair is whether the coefficient is too big;
    * the second digit is whether it is too small. It is possible to get
    * both 0 or both 1s.
    *
    * Example:
    * ______LANES______
    * | 0 | 1 | 2 | 3 |
    * -------------------RUN 1-------------------
    * Precursors : 0 Analysis: 1,0|1,0|0,1|1,0
    * Postcursors: 19 Analysis: 1,0|1,0|1,0|1,0
    * -------------------RUN 2-------------------
    * Precursors : 0 Analysis: 1,0|1,0|1,0|1,0
    * Postcursors: 19 Analysis: 1,0|1,0|1,0|1,0
    * -------------------RUN 3-------------------
    * Precursors : 0 Analysis: 1,0|1,0|1,0|1,0
    * Postcursors: 19 Analysis: 1,0|1,0|1,0|1,0
    *
    * This example shows that both the precursor and postcursor coefficients are
    * too big and should be lowered if possible.
    * Adjusting these coefficients to the best results will then produce the best
    * connection between devices.
    *
    ****************************************************************************/

    Those may improve the stability of your system, but I don't think can achieve 100%. The solution is still as what you did in Answer 4.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 445 points
    Hi Eric,

    Thanks afor you info.
    I have confirmed that I did not switch to low power saving mode.

    Anyway I will add retry for Hyperlink setup.

    Thanks.
  • 0 in reply to lding
    Intellectual 445 points
    Hi Eric,

    BTW, is there any way to disable auto detect polarity feature of Hyperlink and use the user defined polarity to setup Hyperlink?

    thanks.
  • 0 in reply to LI XIANG
    TI__Guru* 95265 points
    Hi,

    The polarity is automatically detected and set by HW.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 445 points
    Hi, Eric,

    One more quesiton about the retry that after I release reset bit, how long will it take to training the Hyperlink lane and linkup?
    What's the timeout value that after wait for this time, if the Hyperlink status is not correct, should I retry?

    thanks s lot.
  • 0 in reply to LI XIANG
    TI__Guru* 95265 points
    Hi,

    >>>>how long will it take to training the Hyperlink lane and linkup?>>>> I don't have exact number for this (You may measure it by first enable Hyperlink on one side, then start a TSCL/TSCH and clear the reset bit then polling the Hyperlink status register to see how long does it take to link up).

    But I think no matter you load the Hyperlink on both ends for the first time or you do a reset for a failed link, you don't have a precise control that both ends clear the reset bit at the same time, correct? Practically, you may wait for a few seconds (3-5) for time-out. You can retry for a few times if the status still not correct.

    Regards, Eric