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DRA76P: GMAC sharing on DRA76x

Oleksandr Baglei
Prodigy 70 points

Part Number: DRA76P

Can we use the GMAC switch in Dual MAC mode shared between IPU (M4) and MPU (A15) on the Jecinto6 SoC? The CPGMAC_SL1 is taken by the IPU as well as the CPGMAC_SL2 taken by the MPU. The common port (P0) is shared by means of the CPDMA channel mapping.
The PoC is to use shared interrupts (RX_THRESH_PULSE, RX_PULSE, TX_PULSE) routed over crossbar to IPU (M4) and MPU (A15) in the same time and filter the interrupts on the both sides for the correct CPDMA channels (MPU uses 0...3 CPDMA channels for TX/RX operations; IPU uses 4...7 CPDMA channels for TX/RX operations).
Can we separate the CPDMA channels for the our processing units (MPU, IPU) and handle it independently by setting the P0_CPDMA_RX_CH_MAP?
Can we handle interrupts on the both sides for the successful CPDMA queues' data movement in parallel (each processing unit check for the own channel status)?
  • 0
    TI__Mastermind 42515 points
    Hi Oleksandr,

    which SDK you use?

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    Prodigy 70 points
    We use
    A15: PSDKLA-3.03 base
    IPU: ndk_2_24_02_31, nsp_gmacsw_4_15_00_00 on top of the bios_6_41_04_54
  • 0 in reply to Oleksandr Baglei
    TI__Expert 8250 points

    Oleksandr 

    Can you review and confirm if you really want to configure and use the switch in dual-emac mode.

    In which case i am assuming , you would want to emulate as if there are 2 independent ports with one being assigned to linux(a5) and the other to rtos(m4)

    For this POC to work the common registers (CPSW core) for control path have to be owned and initialized by one of the cores.

    For Data path you can have the traffic mapped to independent DMA channels and potentially manage from independent cores.

    For Transmit you can have independent Tx DMA channels and use directed mode to send out on respective ports

    For receive need to confirm if we can map the traffic from each port to an independent DMA channel.

    Lastly interrupt handling and acknowledgement from 2 cores will be a challenge, hence using interrupt for one and polling mode from the other core would be better tradeoff

  • 0 in reply to Srirama Govindarajan
    Prodigy 70 points
    Actually, we want configure and use the GMAC switch in the mode (something like ALE_BYPASS) and route the RX traffic from exact port to defined CPDMA channel to distinguish the traffic linked to port1 or port2 and send TX traffic directly to specific port owned by different OS
  • 0 in reply to Oleksandr Baglei
    Prodigy 70 points

    Does the CPDMA process the own channels in parallel or one by one (from channel number 0 to 7)?

  • 0 in reply to Oleksandr Baglei
    TI__Mastermind 27743 points

    CPDMA processes own channels in parallel but there is only one interrupt line/register for all the interrupts. Hence a single core can access interrupt registers.

    You can register interrupts on all cores just to get notification and check if your channel has interrupt raised.

    Another option which can be employed is use of polling instead of an interrupt. You can configure timers at the same interval as of pacing on each core and check of packet Rx/TX. 

    Regards,

    Prasad