Part Number: TDA3
Hi,
we are developing a SYS/BIOS bootloader for our customer on the M4_0 core of the TDA3. It's based on the starteware bootloader, but uses interrupts for the EDMA.
While distributing the sections of the flash image to DDR and IPU_RAM, the EDMA stops triggering the EDMA ISR.
This seems to only happen when copying the resetVecs section to the IPU_RAM. If the sections is not copied, everything works as expected.
- The bootloader is running in OCMC with heap in DDR (memory map for applications is the same, except DDR is used instead of OCMC)
- Only the EDMA and Timer interrupts are enabled
- Only one task is used
More precise (stepping through the code):
- resetVecs are copied to the IPU_RAM
- other sections are copied to DDR
- the next section that should get copied is a valid DDR address
- EDMA transfer is triggered (manual mode)
- interrupt is shown as "pending" in ROV
- Semaphore_pend is called
- ISR does NOT get called
- When pausing, the system hangs on an unused DDR address with a instruction to branch to itself
- The timer interrupt shows "active" in ROV
What we already tried:
- Moving only the distribution function to a standalone application to get rid of other dependencies - same behavior
- Disabling cache - same behavior
- Separating bootloader and application heap - same behavior
- increasing the priority of the EDMA HWI interrupt to eliminate the impact of the timer interrupt - same behavior
- checked if pointers to Hwi_dispatchTable and Hwi_Module__root__V get overwritten - they don't
- changed from hal/timer to dmtimer - same behavior
- many things more...
Questions:
- How can we debug, why the ISR isn't called anymore?
- Where is the start address or register with the ISR address?
- Why is the timer interrupt active when the system has stopped working?
We are thankful for every tip to get this solved!
Best Regards,
Simon
