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TMS320C6654: Clocking

Ramgopal Divakar
Expert 1145 points
Part Number: TMS320C6654
Other Parts Discussed in Thread: CDCE62005,

Hello,

1. Can you recommend a good clocking chip to provide clocks to C6654? I looked at the evaluation board of C6657 and it uses CDCE62005. Is that good to use? I need to provide clock input to CORECLKP/N and DDRCLKP/N. If I don't need PCIe, is it okay to terminate and not provide clocks to PCIECLKP/N?

2. If I use CDCE62005, or equivalent, is it expected for the host to program the clock generator via SPI prior to deassertion of POR? If not can it clock out with some default settings? I'd like to operate the DSP at 850 MHz and I saw the C6657 eval board provides 50 MHz to DDRCLKP/N and 100 MHz to CORECLKP/N. Can I do the same? And if so, how can I default the clocks to these values?

Thanks,

Divakar

  • 0
    Expert 1145 points
    Since I am not using PCIe, I need only two clocks for my core and DDR. I saw the eval board uses 100 MHz and 50 MHz clocks respectively. Can't I just use a differential LVDS clock generator with an enable? It is a lot simpler for C6654. Example Cypress CY2XL11: 100 MHz LVDS Clock Generator for core and CY2XL12 for DDR. I guess I can' terminate the PCIe clock inputs
  • 0 in reply to Ramgopal Divakar
    TI__Guru**** 161600 points

    Hi,

    To answer your questions:

    1. Yes, you can use CDCE62005 as a clock source for your custom board. As for PCIe not being used at all, you can leave all PCIE lanes unconnected the PCIe regulator power pin (VDDR2_PCIe) musts till be connected to the correct supply rail with the appropriate decoupling capacitance applied. As for the clocks you should connect the P to correct power supply rail and the N to GND. All of this is explained in the Hardware Design Guide for Keystone Devices:

    2. As for the clocking of the TMS320C6654 it is explained in details in Chapter 3 Clocking in the Hardware Design Guide for Keystone Devices:

     

    You can choose different clocking scheme for your custom board as long as you comply with the recommendations listed in the Datasheet & Chapter 3 Clocking in the Hardware Design Guide for Keystone Devices.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Expert 1145 points
    Thanks,
    now I need to know what values to set for CORECLKP/N and DDRCLKP/N. I don't have a mechanism to program CDE62005 via SPI as my host processor may take time to boot and also you datasheet doesn't recommend holding PORn for a long time.

    So there are other options to provide LVDS clocking which provide the clocks on power up through straps. I won't enable the clocks until after the power supplies have stabilized.

    Now, can I use 100 MHz, and 50 MHz for CORECLKP/N and DDRCLKP/N respectively. I believe that is what is used on the evaluation board. Will it cover all my internal clocking needs? It isn't clear to me.

    www.ti.com/.../tms320c6654.pdf

    I need UART, SGMII, I2C, SPI and DDR3. PCIe isn't used.

    Do I set the BOOTMODE[12:1] to 011? Table 6-90 on the device datasheet shows the PLLD and PLLM values to get 850 MHz. What about SGMII, will it work? It is not clear to me. I need to boot the DSP via Ethernet. So SGMII has to work. Section 6.24.2.2 says input clocks have to be one of the 3 values 156.25, 250, or 312.5 MHz. Does this mean 100 MHz won't work like I state above?

    DDR - 50 MHz, is this enough to generate 533 MHz for DDR-1066 operation?

    Thanks,
    Divakar
  • 0 in reply to Ramgopal Divakar
    TI__Guru**** 161600 points
    Now, can I use 100 MHz, and 50 MHz for CORECLKP/N and DDRCLKP/N respectively. I believe that is what is used on the evaluation board. Will it cover all my internal clocking needs? It isn't clear to me.

    www.ti.com/.../tms320c6654.pdf

    I need UART, SGMII, I2C, SPI and DDR3. PCIe isn't used.

    Do I set the BOOTMODE[12:1] to 011? Table 6-90 on the device datasheet shows the PLLD and PLLM values to get 850 MHz

    You can refer to the EVM for this.

    You can use:
    100 MHz for CORECLKP/N
    50 MHz for DDR_CLKP/N
    250 (or as you stated 156.25 MHz or 312.5 MHz) for SRIO_SGMII_CLKP/N

    What about SGMII, will it work? It is not clear to me. I need to boot the DSP via Ethernet. So SGMII has to work. Section 6.24.2.2 says input clocks have to be one of the 3 values 156.25, 250, or 312.5 MHz. Does this mean 100 MHz won't work like I state above?

    As I stated in order for SGMII to work you need the SRIO_SGMII_CLKP/N (which can be one of the three, as you state 156.25, 250, or 312.5 MHz). The EVM uses 250 MHz.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1145 points
    Yordan,
    SRIO_SGMII_CLKP/N doesn't seem to exist on C6654. I searched for it in the device datasheet. The hardware design guide refers to it and it is alsop there in C6657. The same pins on C6654 are reserved.

    Am I right?

    So how is the SGMII clock derived?

    Also, with a DDR input clock of 50 MHz, can I get 533 MHz for the DDR and with CORECLK input of 100 MHz, do I set t the BOOTMODE[12:1] to 011? Table 6-90 on the device datasheet shows the PLLD and PLLM values to get 850 MHz

    Regards,
    Divakar
  • 0 in reply to Ramgopal Divakar
    TI__Guru**** 161600 points
    Hi,

    Yes, it seems so. I've notified the design team on this one. They will post their feedback on the other thread you've opened:
    e2e.ti.com/.../788014

    For the moment I am closing this one.

    Best Regards,
    Yordan