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TMS320C6711D: The DSP is locking up

Tom Roberts39
Prodigy 80 points

Part Number: TMS320C6711D

We are using a TMS320C6711DZDP200 in our design..

Our CLKIN has a 150MHz clock input...After continuous operation for an hour or two the System Locks up. We have isolated it down to the DSP and possibly the 150MHz clock input. We do not have a WDT in the design..Our ECLKIN signal is 100MHz.. our ECLKOUT is 100MHz... What I cannot tell is if it is the DSP how can I prove it.. My series terminated resistor is 240 ohms.. My 150MHz is coming from an Altera MAX 10 FPGA.. The 240 is high... The Lockups only occur on a few of our boards.. Any suggestions?

  • 0
    TI__Guru 65405 points
    Hi Tom,

    Do you have some console log? Could you specify what software running on your board?

    Regards,
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 80 points

    Cvetolin,

    Thank you for your response.. My FW engineer replied to your questions with this:

    No, there is no log report for this issue.

    Software details:

    • DSP Software has the Bootloader and the Application code.
    • Bootloader is non-operating system code. It configures the external memory interface, loads itself from flash memory into RAM, begins execution in RAM, initializes the CSL, sets serial port for programming, tests system memory, attempts to load the Application code from Flash to RAM.
    • Application code uses DSP/BIOS as real time micro operating system. Application code has five (5) software interrupts, uses 3 hardware interrupts (2 from DUART and 1 from FPGA at 5 ms), has 5 DSP/BIOS tasks, has 3 queues, 2 pipes (to transmit and receive sound data to/from the CODEC chip for sound). DSP is interfaced with Audio Codec, FPGA, SDRAM, FLASH, DUART, 8 segment LED display, PDM, ADC, DAC, input buttons.

     

    DSP locks up into the Application code.

    This lockup is not occurring on every board.. On a CCA which exhibited the problem we noticed the BGA was shifted in its correct placement.. We removed and replaced the DSP and the lockup still ocurrs but not as soon.. maybe 23 hours into the burn in.. where before the lock up was in the first couple hours.. My concern is whether the 240 series termination resistor on the 150MHz is contributing to the problem. The FW engineer reduce the number of Tasks he was running and the lockup did not occur. Does the load on the CLK150MHZ differ based on what code is being run? We are using 1% resistor values.. the values measured on the failed boards are well within the 1% tolerance..

  • 0 in reply to Tom Roberts39
    TI__Mastermind 30711 points
    Hi Tom,

    Question: If DSP is bad, how can it be proven?
    To rule in or rule out a bad DSP, I recomend a two way board swap experiment: Put a known good device onto a bad board AND put a known bad device onto good board. Does the issue follow the device or follow the board?

    Question: Does load on CLKIN differ based on software being run?
    No the load on the CLKIN input buffer remains the same regardless of software.
    But the fact that software affects stability points towards a signal integrity issue. If you can isolate issue to a particular software routine (like LCD or UART), it might point to a particular trace that is coupling into CLKIN.

    Question: is 240 too high impedance?
    How did you arrive at 240 ohm series term value?
    Does the FPGA use the output clock IO looped-back into the FPGA? Absorbing the reflections bouncing back from the high impedance CLKIN input buffer is one reason why series term resistors are placed close to the output buffer.
    Usually series term resistors are much smaller (on the order of board trace impedance less the output impedance).
    But if the output impedance is closely matched to the trace impedance (and the output clock is not looped back in), then no series term is required at all.
    240ohm series term added with the cap load of the CLKIN buffer could look like an RC filter, filtering out the higher frequencies, resulting in a non-square wave.
    Does the CLKIN signal satisfy the timing requirements in the table titled "timing requirements for CLKIN" on page 69 of the Data manual? Pulse duratin (high/low) of 0.4 cycle minimum where "high" and "low" are above VIH and below VIL thresholds, respectively? A large series term resistor will slow down the edges, allowing more time around the threshold regions, where noise can couple in and glitch or overclock the device.

    For reference, the DSK6713 (same family as C6711) uses a series term resistor of 33 ohms from 50MHz clock source to CLKIN (and ECLKIN). See c6000.spectrumdigital.com/.../6713_dsk_schem.pdf

    I recommend you to measure the CLKIN signal close to the C6711 ball with an active FET probe (the cap load on a passive probe would influence the signal).

    Regards,
    Mark