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CCS/PROCESSOR-SDK-AM65X: The mmap of R5F

Part Number: PROCESSOR-SDK-AM65X


Tool/software: Code Composer Studio

Hello,

I am trying to speed up my R5F program by executing it in the fastest memory which is TCM I supposed.

And I have some questions about the mmap of R5F:

  1. I learned that the start address of TCMB is 0x40000000 from "Table 2-6. MCU_ARMSS Memory Map" in the TRM; however, from the memory layout in linker_r5.lds, the start address of TCMB is 0x41010000 which is not matched with the value in TRM.
  2. What OCMRAM and MSMC3 are? It seems that TRM does not mention these memories.
MEMORY
{
    VECTORS (X)  		: origin=0x41C7F000 length=0x1000
    /*  Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned  */
    RESET_VECTORS (X)  		: origin=0x41C00000 length=0x100
    /* MCU0_R5F_0 local view */
    MCU0_R5F_TCMA_SBL_RSVD (X)	: origin=0x0		length=0x100
    MCU0_R5F_TCMA (X)		: origin=0x100		length=0x8000 - 0x100
    MCU0_R5F_TCMB0 (RWIX)	: origin=0x41010000	length=0x8000

    /* MCU0_R5F_1 SoC view */
    MCU0_R5F1_ATCM (RWIX)  	: origin=0x41400000 length=0x8000
    MCU0_R5F1_BTCM (RWIX) 	: origin=0x41410000 length=0x8000

    /* Fully avaialble for apps. Used by SBL to load SYSFW */
    OCMRAM_LOW 	(RWIX) 		: origin=0x41C00100 length=0x40600 - 0x100	     /* ~257KB */

    /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */
    SBL_RESERVED 	(RWIX) 	: origin=0x41C40600 length=0x60000 - 0x40600	     /* ~126KB */

    /* MCU0 share locations */
    OCMRAM 	(RWIX) 		: origin=0x41C60000 length=0x20000 - 0x1000	     /* ~124KB */

    /* AM65XX M4 locations */
    MSMC3	(RWIX)	 	: origin=0x70000000 length=0xF0000			/* 1MB - 64K */
    /* Reserved for DMSC */
    MSMC3_DMSC (RWIX)		: origin=0x700F0000 length=0x10000			/* 64K */
    MSMC3_H (RWIX)	 		: origin=0x70100000 length=0xF2000			/* 1MB -56K */
    MSMC3_NOCACHE (RWIX)	: origin=0x701F2000 length=0xE000			/* 56K */
    DDR0    (RWIX)  		: origin=0x80000000 length=0x80000000    	/* 2GB */

/* Additional memory settings	*/

}  /* end of MEMORY */

Regards,
Hungwei

  • Hungwei,

    I have checked at Table 2-6 in the latest TRM update and there are a few issues with the update.

    For R5F, I would recommend that you only look at the MCU Domain Memory map in section 2.2.  It is correct that TCMA is remapped from 0x4100_0000 address at reset to 0x0000_00000 after reset but this is because Cortex R5F reset/exception vectors need to be placed at 0x0000_0000 or 0xFFFF_000(Refer section 3.8.8 in Cortex R5 TRM). Cortex R TRM document from ARM indicates the base address of TCMA is configurable using the ATCM Region Register in the core. TI software (GEL, CSL, IPC and bootloader) configures ATCM base address to 0x0000_0000 as we place the reset/exception vectors at base address 0x0000_0000. Also, note ATCM memory is not enabled at power on reset. It is setup using initialization either using GEL or bootloader. 

    The BTCM address in Table 2-6 is incorrect. BTCM memory is enabled at reset and is located at 0x4101_00000 as indicated in the MCU domain memory map table as shown in screen shot below. The OCMRAM in linker command file is the 

    MSMC is the onchip shared memory on the Main domain. To see the base address for region please refer to