We have same DDR3L memory MT41K256M16TW‐107:P as used on AM5728 reference design and we are following the quidelines and design on our layout work. I have tried to find details of trace impedance matching but I'm a bit confused due to following details:
- I checked the EMIF tools spreadsheet and it gives output driver impedance of 34ohm for Addr/ctrl/clk and 48ohm for Data and strobe on ev.kit. These seems to be be also the values I find from SW registers (CTRL_CORE_CONTROL_DDRCACH and ...CONTROL_DDRCH).
- However, trace width on PWB seems to be 94um on all the data, control and address traces and according to my calculations this leads to impedance of 49 to 51ohm depending of the final PWB materials.
- According to DDR3L memory datasheet, with 34ohm driver / 240ohm RZQ, the maximum impedance can be 38.1 or 48.5ohm depending of the driver PU/PD resistor values. So do you know what are the used PU/PD values?
Finally and most importantly, I would like to know what's the used target impedance matching on DDR3L address, data and control lines of PWB design? Is it 48 Ohm?
