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AM5728: DDR3 Compliance Test

Part Number: AM5728

Hi Experts,

Our customer is developing MPU system board with AM5728 and is verifying signal qualities. Recently, customer had done DDR3 Compliance Test, however, their system fails to VIX test for Clock. Customer is using DDR3-SDRAM(DDR3L-1066) which is Micron DDR3 (MT41K256M16TW-107:P).

According to DDR3 specification, customer believe, it would be passed when VIX indicates from 525mv(=675-150) to 825mv(=675+150).

=======

VIX fo Clock

  Pass Limits:-150.000000000 mV to 150.000000000 mV

 =======

Customer tried to look into the reason for this failure and summarized their report. Attached it (DDR3_VIX_FOR_CLOCK_eng.xlsx)

As far as customer investigate, Clock signal was disturbed momentarily and rarely. As the result, customer found out that this signal was caught by tester and it failed.

Customer checked DDR3 power supply/DDR3's signals. Power supply and Data line are stable, however, ADD line and CMD line were disturbed. Customer suppose this behavior causes Clock distortion. Therefore, Customer means, there is possibility that either AM5728 or DDR3 memory is disturbing those lines.

Have you ever hear similar issue so far?

It will be appreciated if you will be able to share your advice/comments on this.

 

I suppose Experts may need the layout data around DDR3, however, customer would like to know there is possibility that either AM5728 is disturbing ADD line and CMD line.

 

Best regards,

Miyazaki

  • Miyazaki,
    ensure that the customer has followed all of the guidelines outlined in the AM5728 datasheet, especially Table 8-12 Routing Specifications and PCB Stackup specifications in section 8.2.2.6. There may be some coupling occurring on the Addr/Command signals

    Regards,
    James
  • Hi James,

    Thanks for your advice. I shared them with our customer and received their feedback.

    Customer referred to Table 8-12 and came up with additional question about CARS323 / CARS324. Regarding Zo, customer interprets that the Zo impedance for CK line is also 50Ohm(min)-75Ohm(Max), as table 8-6 describes Zo.  Is that correct ?

    The reason why customer is asking, is that DDR3 signal line is often wired with 40 ohm. Therefore, customer would like to clarify it just in case. Regarding customer’s board, The termination of CK consists of 49.9 ohm x 2.

    Best regards,

    Miyazaki

  • Miyazaki
    Parameter CARS323 refers to the clock termination resistors, as shown in Figure 8-6. The value of these resistors should be between 49-51 ohms (if Zo=50) If your customer is using 49.9ohms x2, that is correct.  We typically recommend using 1% resistors.

    Parameter CARS324 refers to the Addr/Ctrl termination to VTT, which has looser tolerance between 45-55ohms (if Zo=50ohm),

    Regards,
    James