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AM3352: PLD stall

Yasunori Saito
Intellectual 460 points
Part Number: AM3352


Hi,

My customer has questions about cortex-a8(am335x) PLD instruction, because they has problems in memcopy operation with PLD instruction.

Please teach me about the following.
1. When does a PLD stall occur on cortex-a8?
2. What happens inside of am335x when a PLD stall occur?
3. What happens outside of am335x when a PLD stall occur?
4. Is there a register that counts the number of PLD stalled cycles, similar to the cortex-a9?

Best Regards,
Yasun

  • 0
    TI__Guru* 88330 points
    Yasunori, i'm not aware of any PLD stall monitoring on Cortex-A8. PLD just attempts to prefetch data into cache. What problems with memcpy are your customer seeing? Are they seeing functional or performance issues?

    My understanding is that you need to ensure you provide a cache line aligned memory address in the PLD instruction.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 460 points
    James,

    Thank you for your reply.

    I understand that it need to ensure a cache line aligned memory address in the PLD instruction.
    I have already told about it to them.

    They has functional issues that part of copied data are corrupted.
    They also have doubts about the PLD instruction.

    Is there a good idea to debug the PLD operation?

    Best Regards,
    Yasun
  • 0 in reply to Yasunori Saito
    TI__Guru* 88330 points
    Yasun, i don't have a really good answer here. I'm not sure why you would be getting corrupted data. The only thing i can think of is that there is some sort of cache coherency issue. You can maybe try to move the location of the PLD instruction or change the address that is used to see if you get different behavior. Does the corruption show any pattern?
    Another article on memcpy optimization that i found which might be useful is here on the ARM website: infocenter.arm.com/.../index.jsp

    Regards,
    James