AM3352: About GPMC F15 Timing Parameter

J-breeze

Part Number: AM3352

Hi Champs,

In the datasheet(SPRS717K) page-129, Note no.12 for GPMC F15 timing parameter is described as following.

o AM335x Datasheet [SPRS717K DEC18]
    (http://www.ti.com/litv/pdf/sprs717k)

    - Page 129

      (12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.

So, my question is what "Half cycle" means. I'd like to make sure of it.

Best regards,
J-breeze

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

Hi,

This is half cycle of GPMC_FCLK.

0 J-breeze over 6 years ago in reply to Biser Gatchev-XID

Expert 1105 points

Hi Biser,

Thank you for your reply.
So, J is GPMC_FCLK/2, not GPMC_FCLK for the parameter?

o AM335x Datasheet [SPRS717K DEC18]
    (http://www.ti.com/litv/pdf/sprs717k)

    - Page 129

      (10) J = GPMC_FCLK

Best regards,
J-breeze

0 Mark M over 6 years ago in reply to J-breeze

TI__Mastermind 30110 points

Hi J-breeze,

Note (12) is specific to divide by 1 mode, so GPMC_CLK = (GPMC_FCLK/1) in this case.
It says any data after the first will come out on the falling edge of GPMC_CLK (which equals GPMC_FCLK).

Data is typically latched by the other end of the GPMC bus on the rising GPMC_CLK edge. Whenever the data is launched on one edge (falling) and latched on the other edge (rising edge), it is referred to as half cycle timing.

You might need to tweak WRDATAONADMUXBUS, WRACCESSTIME, and PAGEBURSTACCESSTIME to force the data to be driven onto the bus on the falling GPMC_CLK edge, so it can be latched by the other end on the rising GPMC_CLK edge.

Refer to the experiments performed by the customer on this E2E thread:
https://e2e.ti.com/support/processors/f/791/t/387016

Regards,
Mark

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AM3352: About GPMC F15 Timing Parameter