RTOS/AM5746: About the GPMC Asynchronous Read Access

Hi Rei,

rei said:

Is there a two cycle delay for RDACCESS TIME count to advance after "wait" is denied?

I'm not sure I understand the question clearly. 

The WAIT pin needs to be at a valid level (that is asserted or de-asserted) a minimum of two GPMC clock cycles before RdAccessTime completion to insure a proper dynamic access time control through WAIT pin monitoring. The two GPMC clock cycles advance pipelining are due to the internal synchronization requirements for the WAIT signal. RdAccessTime should be used as a WAIT invalid timing window and should be set to such a value so the WAIT pin is at a valid state two GPMC clock cycles before RdAccessTime completion.

If wait is not asserted two cycles before RDACCESSTIME, then the read will occur at RDACCESSTIME - there is no additional delay.
If wait is asserted two cycles before RDACCESSTIME, then "The wait signal should be de-asserted WaitMonitoringTime+2 FCLK clock cycles before data is sampled"

WAIT monitored as asserted freezes the CycleTime counter.
WAIT monitored as de-asserted unfreezes the CycleTime counter

See related posts:
https://e2e.ti.com/support/processors/f/791/t/187772 
https://e2e.ti.com/support/processors/f/791/t/307113?AM335x-GPMC-WAIT-Pin-Monitoring-Control

rei said:

Does CSRDOFFTIME have to be set to RDACCESSTIME+1 cycle ? 

CSRDOFFTIME and OEOFFTIME and RDCYCLETIME must be AT LEAST RDACCESSTIME + 1 so the data does not get forced off of the bus before the data hold time has been satisfied. The TRM says one cycle after RDACCESSTIME is enough hold time, but confirm with the datasheet for your specific mode.

Hope this helps,
Mark