RTOS/TDA2P-ACD: Invalid Magic String in Boot Image

DDR Stress Test Application
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DDR test - EMIF1 

********************************************************
Running DDR test case 1-- Full memory read/write 
Size of DDR is 0xFFFFFFF
dst address 0x81FFF000
dst address 0x83FFE000
dst address 0x85FFD000
dst address 0x87FFC000
dst address 0x89FFB000
dst address 0x8BFFA000
dst address 0x8DFF9000
dst address 0x8FFF8000 
DDR-- Full memory read/write test is complete 

****************************************************************
Running DDR test case 2 -- Random memory read/write
 
 Random DDR address 0x8E738000 size :0x1000
 Random DDR address 0x8E9D5000 size :0x1000
 Random DDR address 0x8E09F000 size :0x1000
 Random DDR address 0x8EF0E000 size :0x1000
 Random DDR address 0x8F1AB000 size :0x1000
Test count number 0x0
Test count number 0x1 
DDR-- Random memory read/write test is complete 

****************************************************************
Running DDR test case 3 -- Sequential memory read/write
 
Test count number 0x0
Test count number 0x1
DDR-- Sequential memory read/write test is complete 
==============================================================

****************************************************************
Running DDR test case 4 -- Sequential increment pattern 
 
Test count number 0x0
Test count number 0x1
DDR-- Sequential increment pattern test is complete 
==============================================================

DDR test - EMIF2 

********************************************************
Running DDR test case 1-- Full memory read/write 
Size of DDR is 0xFFFFFFF
dst address 0x91FFF000
dst address 0x93FFE000
dst address 0x95FFD000
dst address 0x97FFC000
dst address 0x99FFB000
dst address 0x9BFFA000
dst address 0x9DFF9000
dst address 0x9FFF8000 
DDR-- Full memory read/write test is complete 

****************************************************************
Running DDR test case 2 -- Random memory read/write
 
 Random DDR address 0x8D7D5000 size :0x1000
 Random DDR address 0x8DA72000 size :0x1000
 Random DDR address 0x8DD0F000 size :0x1000
 Random DDR address 0x8D3D9000 size :0x1000
 Random DDR address 0x8D675000 size :0x1000
Test count number 0x0
Test count number 0x1 
DDR-- Random memory read/write test is complete 

****************************************************************
Running DDR test case 3 -- Sequential memory read/write
 
Test count number 0x0
Test count number 0x1
DDR-- Sequential memory read/write test is complete 
==============================================================

****************************************************************
Running DDR test case 4 -- Sequential increment pattern 
 
Test count number 0x0
Test count number 0x1
DDR-- Sequential increment pattern test is complete 
==============================================================

DDR Stress Test Pass

/*
 *******************************************************************************
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 * ALL RIGHTS RESERVED
 *
 *******************************************************************************
 */

/*
 *  ======== mem_segment_definition.xs ========
 *  ======== Single file for the memory map configuration of all cores =========
 */

function getMemSegmentDefinition_external(core)
{
    KB=1024;
    MB=KB*KB;

    DDR3_ADDR                   = 0x80000000;
    DDR3_SIZE                   = 512*MB;

    /*
     * In case of ECC_FFI_INCLUDE, DDR3_BASE_ADDR_1 and DDR3_BASE_SIZE_1
     * are hard-coded in as values of gIpcNonCachedDataAddr and
     * gIpcNonCachedDataSize in Ipu1_0.cfg
     * If this DDR3_BASE_SIZE_0 is changed, update  Ipu1_0.cfg
     */
    DDR3_BASE_ADDR_0            = DDR3_ADDR;
    DDR3_BASE_SIZE_0            = 508*MB;

    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    DDR3_BASE_ADDR_1            = DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0;
    DDR3_BASE_SIZE_1            = DDR3_SIZE - DDR3_BASE_SIZE_0;
    if(core=="ipu1_1" || core=="ipu1_0" || core=="ipu2" || core=="a15_0")
    {
        /*  for ipu1_0, ipu1_1, ipu2 DDR3_BASE_ADDR_1 should be
         *  in non-cached virtual address of
         *  DDR3_BASE_ADDR_1 + 512*MB
         */
       // DDR3_BASE_ADDR_1        = DDR3_BASE_ADDR_1+512*MB;
    }

    DSP1_L2_SRAM_ADDR           = 0x40800000;
    DSP1_L2_SRAM_SIZE           = 288*KB;

    DSP2_L2_SRAM_ADDR           = 0x41000000;
    DSP2_L2_SRAM_SIZE           = 288*KB;

    EVE1_SRAM_ADDR              = 0x42000000;
    EVE1_SRAM_SIZE              = 1*MB;

    EVE2_SRAM_ADDR              = 0x42100000;
    EVE2_SRAM_SIZE              = 1*MB;

    TOTAL_MEM_SIZE              = (DDR3_SIZE);

    /* First 512 MB - cached */
    /* EVE vecs space should be align with 16MB boundary, and if possible try to fit
     * the entire vecs+code+data in 16MB section. In this case a single TLB map would
     * be enough to map vecs+code+data of an EVE.
     * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
     * SR1_FRAME_BUFFER_MEM section is modified.
     */

    /* EVE self-branch instruction block - EVE1_VECS
     * In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.
     * This could overwrites the code/data loaded at 0x80000000.
     * So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for
     * EVE self-branch instruction if no AppImage for EVE.
     * If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,
     * and hence we did not observe any issue.
     * If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,
     * if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000
     */

    EVE1_VECS_SIZE              = 0.5*MB;
    EVE1_CODE_SIZE              =   2*MB;
    EVE1_DATA_SIZE              =13.5*MB;
    EVE2_VECS_SIZE              = 0.5*MB;
    EVE2_CODE_SIZE              =   2*MB;
    EVE2_DATA_SIZE              =12.5*MB;
    NDK_DATA_SIZE               =   4*MB;
    IPU1_1_CODE_SIZE            =   2*MB;
    IPU1_1_DATA_SIZE            =   9*MB;
    IPU1_0_CODE_SIZE            =  10*MB;
    IPU1_0_DATA_SIZE            =  15*MB;
    IPU2_CODE_SIZE              =   2*MB;
    IPU2_DATA_SIZE              =   5*MB;//9*MB;
    DSP1_CODE_SIZE              =   4*MB;
    DSP1_DATA_SIZE              =  47.5*MB;//12.5*MB;
    DSP1_DATA_SIZE_2            =   1*MB;
    DSP2_CODE_SIZE              =   2*MB;
    DSP2_DATA_SIZE              =  6.5*MB;//12.5*MB;
    DSP2_DATA_SIZE_2            =   1*MB;
    /* A15_0_CODE_SIZE reduced since it is not used in .bld file.
     * Check .bld for details. Originally 2 + 14 MB.
     */
    A15_0_DATA_SIZE             =  13*MB;
    if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
    {
        A15_0_DATA_SIZE_INC     =  101*MB /* in MB */
        A15_0_DATA_SIZE         =  (A15_0_DATA_SIZE + A15_0_DATA_SIZE_INC);
    }

    if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes")
    {
        /* Ensure ECC regions are 64kB aligned */
        SR1_FRAME_BUFFER_SIZE       = 285*MB;//309*MB;
        SR1_BUFF_ECC_ASIL_SIZE      =   1*MB;
        SR1_BUFF_ECC_QM_SIZE        =  40*MB;
        SR1_BUFF_NON_ECC_ASIL_SIZE  =   1*MB;
    }
    else
    {
        SR1_BUFF_ECC_ASIL_SIZE      =   4*KB;
        SR1_BUFF_ECC_QM_SIZE        =   4*KB;
        SR1_BUFF_NON_ECC_ASIL_SIZE  =   4*KB;
        SR1_FRAME_BUFFER_SIZE       = 351*MB - (SR1_BUFF_ECC_ASIL_SIZE + SR1_BUFF_ECC_QM_SIZE + SR1_BUFF_NON_ECC_ASIL_SIZE);
        if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
        {
            SR1_FRAME_BUFFER_SIZE   = SR1_FRAME_BUFFER_SIZE - A15_0_DATA_SIZE_INC;
        }
    }

    /* Second 512 MB - non-cached */
    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    REMOTE_LOG_SIZE             =  160*KB;
    SYSTEM_IPC_SHM_SIZE         =  480*KB;
    LINK_STATS_SIZE             =  256*KB;
    HDVPSS_DESC_SIZE            = 1024*KB;
    SR0_SIZE                    =  128*KB;
    OPENVX_SHM_SIZE             =    2*MB;

    if((java.lang.System.getenv("OPENCL_INCLUDE") == "yes"))
    {
        /* when OpenCL is enabled we need more SR0 space
         */
        SR0_SIZE                =  2*MB;
    }


    /* Cached Section */
    /* EVE vecs space should be align with 16MB boundary, and if possible try to fit
     * the entire vecs+code+data in 16MB section. In this case a single TLB map would
     * be enough to map vecs+code+data of an EVE.
     * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
     * SR1_FRAME_BUFFER_MEM section is modified.
     */

    /* EVE self-branch instruction block - EVE1_VECS
     * In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.
     * This could overwrites the code/data loaded at 0x80000000.
     * So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for
     * EVE self-branch instruction if no AppImage for EVE.
     * If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,
     * and hence we did not observe any issue.
     * If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,
     * if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000
     */

    /* Changes for ECC
     * EVE code will run only from non-ECC region
     * All code section should be next to non-ECC region (using EVE section) to
     * allow them to be easily taken out of ECC region for debugging.
     * Make sure DSP1_DATA_ADDR_2 and DSP2_DATA_ADDR_2 are immediately after
     * SR1_BUFF_ECC_QM_ADDR and should be 2*MB in total - this size should
     * be kept constant across all platforms and should match the increment
     * to heapStats.heapSize in utils_xmc_mpu.c
     */
    EVE1_VECS_ADDR             = DDR3_BASE_ADDR_0;
    EVE1_CODE_ADDR             = EVE1_VECS_ADDR             + EVE1_VECS_SIZE;
    EVE1_DATA_ADDR             = EVE1_CODE_ADDR             + EVE1_CODE_SIZE;
    EVE2_VECS_ADDR             = EVE1_DATA_ADDR             + EVE1_DATA_SIZE;
    EVE2_CODE_ADDR             = EVE2_VECS_ADDR             + EVE2_VECS_SIZE;
    EVE2_DATA_ADDR             = EVE2_CODE_ADDR             + EVE2_CODE_SIZE;
    NDK_DATA_ADDR              = EVE2_DATA_ADDR             + EVE2_DATA_SIZE;
    IPU1_1_CODE_ADDR           = NDK_DATA_ADDR              + NDK_DATA_SIZE;
    IPU1_0_CODE_ADDR           = IPU1_1_CODE_ADDR           + IPU1_1_CODE_SIZE;
    IPU2_CODE_ADDR             = IPU1_0_CODE_ADDR           + IPU1_0_CODE_SIZE;
    DSP1_CODE_ADDR             = IPU2_CODE_ADDR             + IPU2_CODE_SIZE;
    DSP2_CODE_ADDR             = DSP1_CODE_ADDR             + DSP1_CODE_SIZE;
    IPU1_1_DATA_ADDR           = DSP2_CODE_ADDR             + DSP2_CODE_SIZE;
    IPU1_0_DATA_ADDR           = IPU1_1_DATA_ADDR           + IPU1_1_DATA_SIZE;
    IPU2_DATA_ADDR             = IPU1_0_DATA_ADDR           + IPU1_0_DATA_SIZE;
    DSP1_DATA_ADDR             = IPU2_DATA_ADDR             + IPU2_DATA_SIZE;
    DSP2_DATA_ADDR             = DSP1_DATA_ADDR             + DSP1_DATA_SIZE;
    A15_0_DATA_ADDR            = DSP2_DATA_ADDR             + DSP2_DATA_SIZE;
    SR1_BUFF_ECC_ASIL_ADDR     = A15_0_DATA_ADDR            + A15_0_DATA_SIZE;
    SR1_BUFF_ECC_QM_ADDR       = SR1_BUFF_ECC_ASIL_ADDR     + SR1_BUFF_ECC_ASIL_SIZE;
    DSP1_DATA_ADDR_2           = SR1_BUFF_ECC_QM_ADDR       + SR1_BUFF_ECC_QM_SIZE;
    DSP2_DATA_ADDR_2           = DSP1_DATA_ADDR_2           + DSP1_DATA_SIZE_2;
    SR1_BUFF_NON_ECC_ASIL_ADDR = DSP2_DATA_ADDR_2           + DSP2_DATA_SIZE_2;
    SR1_FRAME_BUFFER_ADDR      = SR1_BUFF_NON_ECC_ASIL_ADDR + SR1_BUFF_NON_ECC_ASIL_SIZE;

    /* Non Cached Section */
    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    SR0_ADDR                    = DDR3_BASE_ADDR_1;
    REMOTE_LOG_ADDR             = SR0_ADDR              + SR0_SIZE;
    LINK_STATS_ADDR             = REMOTE_LOG_ADDR       + REMOTE_LOG_SIZE;
    SYSTEM_IPC_SHM_ADDR         = LINK_STATS_ADDR       + LINK_STATS_SIZE;
    HDVPSS_DESC_ADDR            = SYSTEM_IPC_SHM_ADDR   + SYSTEM_IPC_SHM_SIZE;
    OPENVX_SHM_ADDR             = HDVPSS_DESC_ADDR      + HDVPSS_DESC_SIZE;

    if ((SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
    {
      throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE));
    }

    if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
    {
        if ((OPENVX_SHM_ADDR + OPENVX_SHM_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
        {
            throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR with OpenVx",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(OPENVX_SHM_ADDR + OPENVX_SHM_SIZE));
        }
    }
    else
    {
        if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
        {
            throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
        }
    }

    if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
    {
      throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
    }

    var memory = new Array();
    var index = 0;

    memory[index++] = ["IPU1_1_CODE_MEM", {
            comment : "IPU1_1_CODE_MEM",
            name    : "IPU1_1_CODE_MEM",
            base    : IPU1_1_CODE_ADDR,
            len     : IPU1_1_CODE_SIZE
        }];
    memory[index++] = ["IPU1_1_DATA_MEM", {
            comment : "IPU1_1_DATA_MEM",
            name    : "IPU1_1_DATA_MEM",
            base    : IPU1_1_DATA_ADDR,
            len     : IPU1_1_DATA_SIZE
        }];
    memory[index++] = ["IPU1_0_CODE_MEM", {
            comment : "IPU1_0_CODE_MEM",
            name    : "IPU1_0_CODE_MEM",
            base    : IPU1_0_CODE_ADDR,
            len     : IPU1_0_CODE_SIZE
        }];
    memory[index++] = ["IPU1_0_DATA_MEM", {
            comment : "IPU1_0_DATA_MEM",
            name    : "IPU1_0_DATA_MEM",
            base    : IPU1_0_DATA_ADDR,
            len     : IPU1_0_DATA_SIZE
        }];
    memory[index++] = ["IPU2_CODE_MEM", {
            comment : "IPU2_CODE_MEM",
            name    : "IPU2_CODE_MEM",
            base    : IPU2_CODE_ADDR,
            len     : IPU2_CODE_SIZE
        }];
    memory[index++] = ["IPU2_DATA_MEM", {
            comment : "IPU2_DATA_MEM",
            name    : "IPU2_DATA_MEM",
            base    : IPU2_DATA_ADDR,
            len     : IPU2_DATA_SIZE
        }];
    memory[index++] = ["DSP1_CODE_MEM", {
            comment : "DSP1_CODE_MEM",
            name    : "DSP1_CODE_MEM",
            base    : DSP1_CODE_ADDR,
            len     : DSP1_CODE_SIZE
        }];
    memory[index++] = ["DSP1_DATA_MEM", {
            comment : "DSP1_DATA_MEM",
            name    : "DSP1_DATA_MEM",
            base    : DSP1_DATA_ADDR,
            len     : DSP1_DATA_SIZE
        }];
    memory[index++] = ["DSP1_DATA_MEM_2", {
            comment : "DSP1_DATA_MEM_2",
            name    : "DSP1_DATA_MEM_2",
            base    : DSP1_DATA_ADDR_2,
            len     : DSP1_DATA_SIZE_2
        }];

    memory[index++] = ["DSP2_CODE_MEM", {
            comment : "DSP2_CODE_MEM",
            name    : "DSP2_CODE_MEM",
            base    : DSP2_CODE_ADDR,
            len     : DSP2_CODE_SIZE
        }];
    memory[index++] = ["DSP2_DATA_MEM", {
            comment : "DSP2_DATA_MEM",
            name    : "DSP2_DATA_MEM",
            base    : DSP2_DATA_ADDR,
            len     : DSP2_DATA_SIZE
        }];
    memory[index++] = ["DSP2_DATA_MEM_2", {
            comment : "DSP2_DATA_MEM_2",
            name    : "DSP2_DATA_MEM_2",
            base    : DSP2_DATA_ADDR_2,
            len     : DSP2_DATA_SIZE_2
        }];

    memory[index++] = ["NDK_MEM", {
            comment : "NDK_MEM",
            name    : "NDK_MEM",
            base    : NDK_DATA_ADDR,
            len     : NDK_DATA_SIZE
        }];
    memory[index++] = ["A15_0_DATA_MEM", {
            comment : "A15_0_DATA_MEM",
            name    : "A15_0_DATA_MEM",
            base    : A15_0_DATA_ADDR,
            len     : A15_0_DATA_SIZE
        }];

    memory[index++] = ["EVE1_VECS_MEM", {
            comment : "EVE1_VECS_MEM",
            name    : "EVE1_VECS_MEM",
            base    : EVE1_VECS_ADDR,
            len     : EVE1_VECS_SIZE
        }];
    memory[index++] = ["EVE1_CODE_MEM", {
            comment : "EVE1_CODE_MEM",
            name    : "EVE1_CODE_MEM",
            base    : EVE1_CODE_ADDR,
            len     : EVE1_CODE_SIZE
        }];
    memory[index++] = ["EVE1_DATA_MEM", {
            comment : "EVE1_DATA_MEM",
            name    : "EVE1_DATA_MEM",
            base    : EVE1_DATA_ADDR,
            len     : EVE1_DATA_SIZE
        }];
    memory[index++] = ["EVE2_VECS_MEM", {
            comment : "EVE2_VECS_MEM",
            name    : "EVE2_VECS_MEM",
            base    : EVE2_VECS_ADDR,
            len     : EVE2_VECS_SIZE
        }];
    memory[index++] = ["EVE2_CODE_MEM", {
            comment : "EVE2_CODE_MEM",
            name    : "EVE2_CODE_MEM",
            base    : EVE2_CODE_ADDR,
            len     : EVE2_CODE_SIZE
        }];
    memory[index++] = ["EVE2_DATA_MEM", {
            comment : "EVE2_DATA_MEM",
            name    : "EVE2_DATA_MEM",
            base    : EVE2_DATA_ADDR,
            len     : EVE2_DATA_SIZE
        }];
    memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
            comment : "SR1_FRAME_BUFFER_MEM",
            name    : "SR1_FRAME_BUFFER_MEM",
            base    : SR1_FRAME_BUFFER_ADDR,
            len     : SR1_FRAME_BUFFER_SIZE
        }];
    memory[index++] = ["SR1_BUFF_ECC_ASIL_MEM", {
            comment : "SR1_BUFF_ECC_ASIL_MEM",
            name    : "SR1_BUFF_ECC_ASIL_MEM",
            base    : SR1_BUFF_ECC_ASIL_ADDR,
            len     : SR1_BUFF_ECC_ASIL_SIZE
    }];
    memory[index++] = ["SR1_BUFF_ECC_QM_MEM", {
            comment : "SR1_BUFF_ECC_QM_MEM",
            name    : "SR1_BUFF_ECC_QM_MEM",
            base    : SR1_BUFF_ECC_QM_ADDR,
            len     : SR1_BUFF_ECC_QM_SIZE
    }];
    memory[index++] = ["SR1_BUFF_NON_ECC_ASIL_MEM", {
            comment : "SR1_BUFF_NON_ECC_ASIL_MEM",
            name    : "SR1_BUFF_NON_ECC_ASIL_MEM",
            base    : SR1_BUFF_NON_ECC_ASIL_ADDR,
            len     : SR1_BUFF_NON_ECC_ASIL_SIZE
    }];
    memory[index++] = ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }];
    memory[index++] = ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }];
    memory[index++] = ["REMOTE_LOG_MEM", {
            comment : "REMOTE_LOG_MEM",
            name    : "REMOTE_LOG_MEM",
            base    : REMOTE_LOG_ADDR,
            len     : REMOTE_LOG_SIZE
        }];
    memory[index++] = ["LINK_STATS_MEM", {
            comment : "LINK_STATS_MEM",
            name    : "LINK_STATS_MEM",
            base    : LINK_STATS_ADDR,
            len     : LINK_STATS_SIZE
        }];
    memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
            comment : "SYSTEM_IPC_SHM_MEM",
            name    : "SYSTEM_IPC_SHM_MEM",
            base    : SYSTEM_IPC_SHM_ADDR,
            len     : SYSTEM_IPC_SHM_SIZE
        }];

    xdc.print("# !!! Core is [" + core + "] !!!" );

    memory[index++] = ["DSP1_L2_SRAM", {
            comment: "DSP1_L2_SRAM",
            name: "DSP1_L2_SRAM",
            base: DSP1_L2_SRAM_ADDR,
            len:  DSP1_L2_SRAM_SIZE
        }];
    memory[index++] = ["DSP2_L2_SRAM", {
            comment: "DSP2_L2_SRAM",
            name: "DSP2_L2_SRAM",
            base: DSP2_L2_SRAM_ADDR,
            len:  DSP2_L2_SRAM_SIZE
        }];

if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
{
/* This is a dummy section needed for OpenCL */
        L1DSRAM_ADDR = 0x00F00000;
        L1DSRAM_SIZE = 0x00008000;
        OCL_LOCAL_ADDR = 0x0083B000;
        OCL_LOCAL_SIZE = 0x00004000;
        memory[index++] = ["L1DSRAM", {
            comment: "L1DSRAM",
            name: "L1DSRAM",
            base: L1DSRAM_ADDR,
            len:  L1DSRAM_SIZE
        }];

}

    if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
    {
        memory[index++] = ["OPENVX_SHM_MEM", {
                comment: "OPENVX_SHM_MEM",
                name: "OPENVX_SHM_MEM",
                base: OPENVX_SHM_ADDR,
               len:  OPENVX_SHM_SIZE
        }];
    }

    return (memory);
}

/*******************************************************************************
*  file name: a15_0.cfg
*  Set A15 core 0 specific configuration
*
*******************************************************************************/

var CurrentPlatform = java.lang.System.getenv("PLATFORM");
var DualA15_smpbios = java.lang.System.getenv("DUAL_A15_SMP_BIOS");
var OpenCL = java.lang.System.getenv("OPENCL_INCLUDE");
var OpenCV = java.lang.System.getenv("ENABLE_OPENCV");

xdc.print("# !!! Current build platform is [" + CurrentPlatform + "] !!!" );

xdc.loadPackage('ti.sysbios').profile = "release";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/BIOS_common.cfg");

/* root of the configuration object model */
var Program = xdc.useModule('xdc.cfg.Program');

xdc.useModule('ti.sysbios.gates.GateHwi');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
if(OpenCL=="yes")
{
var SecondsClock = xdc.useModule('ti.sysbios.hal.SecondsClock');
}

BIOS.cpuFreq.hi = 0;
BIOS.cpuFreq.lo = 750000000; /* 750 MHz */

if(DualA15_smpbios=="yes")
{
   BIOS.smpEnabled = true;
}
else
{
   BIOS.smpEnabled = false;
}

/*
 *  ======== IPC Configuration ========
 */
Program.global.procName = "HOST";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/IPC_common.cfg");


var NdkProcToUse = java.lang.System.getenv("NDK_PROC_TO_USE");

if(NdkProcToUse=="a15_0")
{
   xdc.print("# !!! Linking to NDK !!!" );
   xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/NDK_config.cfg");
}

/*
 *  ======== Operating System Configuration ========
 */

/* no rts heap */
Program.heap = 0;
Program.argSize = 100;  /* minimum size */
if(OpenCL=="yes")
{
    Program.stack = 0x4000;
}
else
{
    Program.stack = 0x4000;
}

/* create a default heap */
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams = new HeapMem.Params();
if(OpenCL=="yes")
{
    heapMemParams.size = 0x6000000;
}
else
{
    heapMemParams.size = 0x600000;
}

var Memory = xdc.useModule('xdc.runtime.Memory');
Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
if(OpenCL=="yes")
{
    Memory.defaultHeapSize = 0x6000000;
}

/* Enable Cache */
if(DualA15_smpbios=="yes")
{
   var Cache = xdc.useModule('ti.sysbios.family.arm.a15.smp.Cache');
}
else
{
   var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
}
Cache.enableCache = true;

/***********************************************
 *              MMU Configuration              *
 ***********************************************/
var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
Mmu.enableMMU = true;

/******************************************************************************
 *
 * SYS/BIOS assigns the following defaults to MAIR0 ATTR0, ATTR1 and ATTR2:
 *
 * ATTR0 -> 0x44 (mark memory region as non-cacheable normal memory)
 * ATTR1 -> 0x00 (mark memory region as device memory, i.e. strongly
 * ordered and non-cacheable)
 * ATTR2 -> 0xFF (mark memory region as normal memory, RW cacheable and
 * RW allocate)
 ******************************************************************************
 */



// descriptor attribute structure
var attrs0 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs0);

attrs0.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
attrs0.noExecute = true;                   // not executable
attrs0.accPerm = 0;                        // read/write at PL1
attrs0.shareable = 2;                      // shareable
attrs0.attrIndx = 1;                       // strongly ordered and non-cacheable

// Set the descriptor for each entry in the address range
// NOTE: Currently mapping all region as non-cacheable, device memory.
//If in future application want to use OCMC memories it needs to remove corresponding MMU entries from below and make it cacheable.
for (var i=0x40000000; i < 0x60000000; i = i + 0x00200000) {
    // Each 'BLOCK' descriptor entry spans a 2MB address range
    Mmu.setSecondLevelDescMeta(i, i, attrs0);
}

// descriptor attribute structure
var attrs1 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs1);
attrs1.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
attrs1.shareable = 2;                      // sharerable
attrs1.attrIndx = 2;                       // Cached, normal memory

// Set the descriptor for each entry in the address range
for (var i=0x80000000; i < 0x90000000; i = i + 0x00200000) {
    // Each 'BLOCK' descriptor entry spans a 2MB address range
    Mmu.setSecondLevelDescMeta(i, i, attrs1);
}

// descriptor attribute structure
var attrs2 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs2);
attrs2.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
attrs2.shareable = 2;                      // sharerable
attrs2.attrIndx = 0;                       // Non-cache, normal memory

// Set the descriptor for each entry in the address range
for (var i=0x90000000; i < 0xA0000000; i = i + 0x00200000) {
    // Each 'BLOCK' descriptor entry spans a 2MB address range
    Mmu.setSecondLevelDescMeta(i, i-0x10000000, attrs2);
}

// Region for NDK packet data buffers.
for (var i = 0; i < Program.cpu.memoryMap.length; i++)
{
    memSegment = Program.cpu.memoryMap[i];
    if (memSegment.name == "NDK_MEM")
    {
        var attrs3 = new Mmu.DescriptorAttrs();
        Mmu.initDescAttrsMeta(attrs3);
        attrs3.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
        attrs3.noExecute = true;                   // not executable
        attrs3.shareable = 2;                      // shareable
        attrs3.accPerm = 0;                        // read/write at PL1
        attrs3.attrIndx = 2;                       // Mark mem regions as cached, normal memory

        // Set the descriptor for each entry in the address range
        for (var j=memSegment.base; j < (memSegment.base + memSegment.len); j = j + 0x00200000)
        {
            // Each 'BLOCK' descriptor entry spans a 2MB address range
            Mmu.setSecondLevelDescMeta(j, j, attrs3);
        }
    }
}

/* .text is allocated as per "codeMemory" defined in .bld file.
 * .data, .stack, .bss, .sysmem, etc are allocated as per
 * "dataMemory" defined in .bld file */
Program.sectMap[".bss:extMemNonCache:remoteLogCoreShm"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:hcfResourceTable"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:ipcShm"]           = "SYSTEM_IPC_SHM_MEM";
Program.sectMap[".bss:extMemNonCache:linkStats"]        = "LINK_STATS_MEM";
if (java.lang.System.getenv("OPENVX_INCLUDE") == "yes")
{
    Program.sectMap[".bss:extMemNonCache:tiovxObjDescShm"] = "OPENVX_SHM_MEM";
}

Program.sectMap[".bss:NDK_PACKETMEM"]                   = "NDK_MEM";
Program.sectMap[".bss:NDK_MMBUFFER"]                    = "NDK_MEM";

var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");


/* Exception hook function */
var ExceptionA15 = xdc.useModule('ti.sysbios.family.arm.exc.Exception');

/* enable print of exception handing info */
ExceptionA15.excHookFunc ='&Utils_a15ExceptionHookFxn';
ExceptionA15.enableDecode=true;

/* XDC runtime function */
var Error = xdc.useModule("xdc.runtime.Error");
Error.raiseHook = "&Utils_commonErrorRaiseHook";

/* Add an idle thread 'Utils_idleFxn' that monitors interrupts. */
var Idle = xdc.useModule("ti.sysbios.knl.Idle");

if (DualA15_smpbios == "yes")
{
    Idle.addCoreFunc('&Utils_idleFxn', 0);
    Idle.addCoreFunc('&Utils_idleFxn', 1);
}
else
{
    Idle.addFunc('&Utils_idleFxn');
}

/* Assign GPTimer2 to be used for BIOS Clock 1-ms tick */
/***********************************************
 *          CLOCK Module Configuraion          *
 ***********************************************/
var Clock = xdc.useModule("ti.sysbios.knl.Clock");

if(OpenCL=="yes")
{
    Clock.tickMode = Clock.TickMode_PERIODIC;
}
else
{
    Clock.tickMode = Clock.TickMode_PERIODIC;
    Clock.tickSource = Clock.TickSource_USER;
}

/***********************************************
*           Timer Module Configuraion         *
***********************************************/
/* Assign GPTimer2 to be used for Timestamp */
/* Set to 1-ms Tick and Enable Wakeup for OVF interrupt */
var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
var timerParams = new Timer.Params();
timerParams.period = 1000;
timerParams.twer.ovf_wup_ena = 1;
timerParams.tiocpCfg.emufree = 1;
timerParams.tsicr.posted = 0;
/* Timer ID = 1 for GPTimer2 and input clock runs at 20 MHz */
Timer.intFreqs[1].hi = 0;
Timer.intFreqs[1].lo = 20000000;
Timer.create(1, '&mainA15TimerTick', timerParams);

/* Assign GPTimer3 to be used for Timestamp */
/* Timer ID = 2 for GPTimer3 and input clock runs at 20 MHz */
var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
var timerParams2 = new DMTimer.Params();
timerParams2.tsicr.posted = 0;
DMTimer.intFreqs[2].hi = 0;
DMTimer.intFreqs[2].lo = 20000000;
var DMTimestampProvider = xdc.useModule("ti.sysbios.timers.dmtimer.TimestampProvider");
DMTimestampProvider.timerId = 2;
DMTimestampProvider.useClockTimer = false;
var Timestamp = xdc.useModule("xdc.runtime.Timestamp");
Timestamp.SupportProxy = DMTimestampProvider;

/* Indicate GPT2 & GPT3 are used */
var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
TimerSupport.availMask = 0x0006;

/* In order to check how much percentange of Idle time the CPU is in Low power */
var LocalTimestampProvider = xdc.useModule('ti.sysbios.family.arm.a15.TimestampProvider');

/* Add POSIX Support */
if(OpenCV=="yes")
{
    var Settings = xdc.useModule('ti.sysbios.posix.Settings');
    Settings.supportsMutexPriority = true;
}

if(OpenCL=="yes")
{
    var Settings = xdc.useModule('ti.sysbios.posix.Settings');
    Settings.supportsMutexPriority = true;
    xdc.global.oclProcName = "HOST";
    var OCL = xdc.useModule('ti.opencl.OpenCL');
    OCL.computeUnitList = "0";
    OCL.OCL_ipc_customized = true;
    OCL.OCL_memory_customized =true;
    OCL.OCL_HOSTPROG_base = Program.cpu.memoryMap["A15_0_DATA_MEM"].base;
    OCL.OCL_HOSTPROG_len  = Program.cpu.memoryMap["SR1_FRAME_BUFFER_MEM"].base - Program.cpu.memoryMap["A15_0_DATA_MEM"].base
                            + Program.cpu.memoryMap["SR1_FRAME_BUFFER_MEM"].len;
    OCL.OCL_GLOBAL_base   = Program.cpu.memoryMap["EVE2_CODE_MEM"].base;
    OCL.OCL_GLOBAL_len    = Program.cpu.memoryMap["EVE2_CODE_MEM"].len;
    OCL.OCL_LOCAL_base    = Program.cpu.memoryMap["OCMC_RAM2"].base;
    OCL.OCL_LOCAL_len     = Program.cpu.memoryMap["OCMC_RAM2"].len;
}