RTOS/AM5728: How to reduce the delay from PC(RootComple) to negate INTA for PCI Express of AM5728

Hi,

From AM5728 TRM:
24.9.4.6.2.1.2 Legacy PCI Interrupt Transmission (EP mode only)
Writing 0b1 to TI wrapper register PCIECTRL_TI_CONF_INTX_ASSERT[0] ASSERT_F0 bit sends an
ASSERT message on the “interrupt pin” specified in the config header space.
Writing 0b1 to TI wrapper register PCIECTRL_TI_CONF_INTX_DEASSERT[0] DEASSERT_F0 bit will
send a DEASSERT message on the “interrupt pin” specified in the config header space.
A status of the virtual “interrupt line” is available by reading out either bitfield.
NOTE: This status is just a local record of the last message sent, it is not the result of any feedback
from the PCIe fabric, since messages are posted, no response is generated. For that reason,
the PCIe protocol does not guarantee the coherence between assertion and deassertion
INTx messages, that means that it’s up to the application to ensure that the INTx assertion
has been seen by the RC before sending the deassertion, and vice versa.

This talks about the PCIE EP with AM5728. The same rule applies to PCIE RC using a Windows PC. From your diagram,
4: Assert INTA, your PC's CPU gets the INTA from EP and starts the ISR

Your ISR seems do the following:
- GPMC writes over PCIE (steps 5, 6, 7)
- EP negate INTA (step 8), does step 8 depending on GPMC write finishing in step 7
- Deassert INTA all the way to RC (steps 9, 10, 11)

My suggestion, once you entered ISR in the RC side, can you first deassert INTA without waiting for the GPMC write, EP side deassert, all the way back to RC? Certainly in this order, the RC de-asserted INTA, then EP de-assert INTA after a while. But you don't need to keep them in sync.

Regards, Eric