• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 468 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AMIC120: bit 30 and bit 31 of R31 register in PRU-ICSS

U-SK
Genius 5840 points
Part Number: AMIC120

Hello.

1.After bit 30 or bit 31 of R31 register in PRU-ICSS is set by system event, when is these bit cleared?

2.If multiple system events are mapped to host-0, could you tell me the procedure to know what event occurred when R31 bit 30 is set?

Regards,

U-SK

  • 0
    TI__Genius 15900 points

    Hi U-SK,

    1.  This is described in section 30.4.2.3.6 "Interrupt Status Clearing" of the device TRM.  In short, you'll need to first service (or clear) the event sources for all pending interrupts that are mapped to and enabled for Host0/1.  Then, the corresponding event status bit in the PRU-ICSS INTC registers (i.e. INTC_SECR[1-2]) will need to be cleared.  

    The PRU Software Support package has several examples using the INTC.  Below are a few that you might find interesting:

    • pru_cape/pru_fw/PRU_Audio - PRU is interrupted by IEP timer
    • labs/lab_4/solution/button_led_1 - PRU interrupted by the other PRU core

    2. There are a few ways to determine which event caused the interrupt:  

    a. You can check the INTC_HIPIR[0-7] register to see the highest priority pending interrupt for a given host.  (Note, the device TRM details how to update the INTC's prioritization.  See section 30.4.2.3.4.2 "Interrupt Prioritization.")

    b. Alternatively, you can read the INTC_SECR[0-1] registers to identify all the pending interrupts.

    Regards,

    Melissa