Linux/AM3359: SPL not loading after DDR configuration

Part Number: AM3359

Tool/software: Linux

Hello all,

                               I'm working on a custom board based on am3359 ice v2.I followed the DDR3 emif configuration guide an configured the DDR(MT41K256M16).I also ran the .gel file in CCS to test the ram and it passed the integrity test.I modifed ddr_defs.h with the same timing and values but spl is not loading."CCCCC" is printing before spl is loaded through xmodem.But nothing after that.How can I debug this?

                 We have enabled debug prints in SPL.If DDR configuation is wrong will SPL be able to print any debug messages?

We are using 25MHz input clock and DDR is operated at 400MHz.This is our modified gel file.

5432.TMDXICE3359.gel

7217.ddr_defs.h

Regards,

Murugan S

Hi Biser,
We have developed another similar board in which when we load the u-boot-spl.bin some prints like "Uboot SPL" would come.In this board there is no prints after the spl.bin is loaded.If DDR is not configured properly will SPL be able to print any debug messages?

Regards,
Murugan S

Hi Biser,

We have one working board(but with different DDR trace lengths).We intentionally messed up the ddr timings in ddr_defs.h to verify your statement.And with the wrong DDR timing on the working board no SPL  prints were coming.

From my understanding I should modify the following macros in u-boot source:

#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4EB
#define MT41J128MJT125_EMIF_TIM2_400MHz 0x266B7FDA
#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F867F
#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C05932

#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x1
#define MT41J128MJT125_RD_DQS_400MHz 0x03a
#define MT41J128MJT125_WR_DQS_400MHz 0x0be
#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x0ed
#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x116

Is modifying these macros enough for correct DDR configuration?or did I miss anything?


Regards,
Murugan S