Part Number: AM4378
Tool/software: Linux
Recently, we used TI AM437x chip for freertos transplantation, and encountered some problems in the process of transplantation
1.Bit0 is described as secure in register ICDDCR
When INTCInit(INTC_NON_SECURE_MODE) is initialized for gic.c
{
/* Enable NS interrupts in Non-secure mode */
ctrlConfigval = GIC_CPU_ICCICR_NS_ENABLE_MASK; ------Why use bit0
}
/* Enable CPU interface to signal the interrupt */
HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCICR), ctrlConfigval);
#define GIC_CPU_ICCICR_NS_ENABLE_MASK (0x00000001U)
2.Configure the priority of registers
/* Find the priority levels implemented */
for(intrNum = 0; intrNum < gicInst->maxValidIntr; intrNum++)
{
if (isIntrSupported(intrNum))
{
HW_WR_REG8((distBaseAddr + GIC_DIST_PRIORITY_REG_B(intrNum)), 0xFF); -----Write 0XFF and read back the value 0xF0. Why is this value?How do I configure a minimum priority of 32?
PriorityStep = HW_RD_REG8(distBaseAddr + GIC_DIST_PRIORITY_REG_B(intrNum));
/* Extract the priority level */
gicInst->noPriorityStep = ((~PriorityStep) & 0x0F) + 1; -------What does this mean?This value is always 16, resulting in only integer multiples of 16 being configured at interrupt priority
break;
}
}
/* Validate the parameters. SGI can't be configured */
if ((intrNum > GIC_MAX_INTR_NO) ||
(pIntrParams->priority > GIC_CPU_INTF_MIN_PRI) ||
(pIntrParams->pFnIntrHandler == NULL) ||
/* Priority value is not given in the levels supported */
(pIntrParams->priority % gicInst->noPriorityStep != 0))
status = E_INVALID_PARAM;
3.The value of IT lines number in the register ICDICTR reads 111,256 interrupt levels. Can this value be changed?
4.How to use the register ICCBPR?
else
{
/* Non-Secure BPR */
HW_WR_REG32((cpuIntfBaseAddr + GIC_CPU_ICCBPR), -----INTC_NON_SECURE_MODE，The GIC_CPU_ICCBPR register is used but the GIC_CPU_ICCABPR is not
gicInst->gicConfig.nonSecureBinaryPoint);
}
