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Linux/AM4372: DDR3 initialization for custom board

M.Ucar
Prodigy 210 points
Part Number: AM4372

Tool/software: Linux

Hello Dear TI-Team,

we have an issue with our DDR3 Initialization. Out Custom-Board is based on the SK-EVM Board and have the Micron MT41K128M16JT-125 XIT:K (2GB). www.micron.com/.../mt41k128m16jt-125

I have first used an predefined configuration oft the MT41J128M16JT-125 from arch/arm/include/asm/arch-am335x/ddr_defs.h which already worked fine. But on different temperature my board is either stuck after booting the kernel ... done or crashes randomly while booting the kernel. This Issue occurs only on high temperatures. So I tought that the ddr3-timing could be wrong.

I have tried to set the ddr3 timing with the help of the EMIF-Tool, but the ddr3 doesnt work with the emif configurations yet. Could you please help me out?

1.) Why I cant set the CAS and CWL Latency?

2.) Are the phy ctrl register correct?

DDR3_EMIF_CONFIG.xlsx

Thanks for your help!

  • 0
    Prodigy 210 points 
    const struct emif_regs ddr3_emif_regs_400Mhz_production = {
    .sdram_config               = 0x61A052B2, /*0x638413B2*/
    .ref_ctrl                   = 0x0000093B,
    .sdram_tim1                 = 0xE888A2D3, /* change for difference in MHz*/
    .sdram_tim2                 = 0x36337FDA,
    .sdram_tim3                 = 0x5F7F826F, /* change for difference in MHz*/
    .read_idle_ctrl             = 0x00050000,
    .zq_config                  = 0x50077D33,
    .temp_alert_config          = 0x0,
    .emif_ddr_phy_ctlr_1        = 0x00048008,
    .emif_ddr_ext_phy_ctrl_1    = 0x00040100,
    .emif_ddr_ext_phy_ctrl_2    = 0x00000000,
    .emif_ddr_ext_phy_ctrl_3    = 0x00000000,
    .emif_ddr_ext_phy_ctrl_4    = 0x00000000,
    .emif_ddr_ext_phy_ctrl_5    = 0x00000000,
    .emif_rd_wr_exec_thresh     = 0x80000000,
    .emif_prio_class_serv_map   = 0x80000001,
    .emif_connect_id_serv_1_map = 0x80000094,
    .emif_connect_id_serv_2_map = 0x00000000,
    .emif_cos_config            = 0x000FFFFF,
    .emif_rd_wr_lvl_rmp_ctl     = 0x80000000,
};

    the code above are the resulted config in my board.c file

  • 0 in reply to M.Ucar
    TI__Guru* 87040 points
    The file you attached seems to be corrupted. Can you download the spreadsheet from ti.com again and fill it in according to your board parameters and memory?
    One thing to note is that at higher temps (typically above 85C), DDR3 requires a faster refresh rate. Check your DDR3 datasheet for more information. You would have to increase the refresh rate if your design is operating above that threshold.

    Regards,
    James
  • 0 in reply to M.Ucar
    TI__Guru* 87040 points
    Based on the DDR3 datasheet, a few changes need to be made to the spreadsheet:

    -In DDR Timings, change tRC=48.75ns. This is what is specified in the speed bin table for DDR3-1600
    -In DDR Timings, change tFAW=40ns. Table 75 in the DDR3 datasheet shows this for DDR3-1600, 2KB page size, which is the device you are using
    -In DDR Timings, change tRRD= 4tCK or 7.5ns. This is also shown in Table 75. This does not change the result you previously had, but I'm just trying to stay consistent with the datasheet values.
    -In DDR Timings, change tRFC=160. This is also shown in Table 75 for a DDR3-1600 2Gb device

    Try with the above fixes. Also, as i previously said, if you are operating above 85C, you will need to adjust the refresh rate as discussed in the DDR3 datasheet

    Regards,
    James