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Linux/AM5726: can't boot linux on AM5726

chris montoya
Prodigy 100 points
Part Number: AM5726
Other Parts Discussed in Thread: AM5728, , PMP, DRA752

Tool/software: Linux

 Hello, Our team has been trashing for a month trying to boot linux on this processor. This is now gating real revenue for our company.  We really need TI's help! My coworkers Devon Clark and Christine Nason, have posted north of 50 posts in the last month trying to resolve the issue we need a person from TI that is intimately involved in the Linux board support package to help us please.

Now for are issue: We have a AM5728 EVM board that works we can boot it we can our software with it prototype. We built our own AM5728 board and we can't boot it. Here is a complete list of the deltas between our board and the EVM board. Can one of your experts look at this and tell us how to configure linux to boot properly? Can we setup a webex to talk it through live with some one ?

Our board has no EEPROM

PMIC INT mapped to different I/O

PMIC mapped from I2C1 to I2C2

LDO1 (1.8V) not hooked up to processor, were using 3.3V for the SD card

AM5728 vs AM5726 (no multimedia/video support on AM5726)

DDR 2GB vs 4GB DDR on our board does not support ECC

Our board added 5 port switch, 3 port switch, POE chip,

Persistent RTC chip, GPIO

Our board removed Quad SPI Flash,

No devices on PCI bus,

no LED driver chip,

no video/camera related chip 

  • 0
    TI__Guru*** 125430 points
    Chris,

    I suspect there are a number of issues that need to be worked through. For this particular thread, I suggest that we stay focused on simply being able to reliably get to a u-boot prompt. Once we get to that point I ask that you please mark this as "resolved" and start new threads for additional issues.

    Let's start with some fundamentals:

    Hardware
    1. Do you see RSTOUTn going high when you boot the board?
    2. What are you seeing on the console when you try to boot? Nothing?
    3. Why did you change the PMIC mappings and the LDO1 hookup? Those sorts of "small" changes tend to create more trouble than you'd expect. I don't know if that's for sure responsible, but it wouldn't surprise me.
    4. Are you booting from SD card? eMMC?

    Software
    A. Given that you have no EEPROM, have you hard-coded all the defines for board_is_XYZ to fixed values? Otherwise u-boot will bail given that it won't find an EEPROM and won't even know which UART to use as the console.
    B. Have you download the app note and filled out the accompany spreadsheet EMIF Tools: http://www.ti.com/sprac36
    C. Have you made the necessary adjustments for the I2C and SD card?
    D. Do you know if you MLO has successfully been loaded? I'm trying to determine whether we're debugging a boot issue (i.e. ROM code) or a u-boot software issue.

    Diagnostics

    I have some scripts for Code Composer Studio that can help us quickly get to the root of some of the issues I've outlined above. The general process for running these scripts is described here:

    git.ti.com/.../README

    In your particular instance, there are several scripts which you should run:

    git.ti.com/.../am57xx-boot.dss
    git.ti.com/.../am57xx-ctt.dss
    git.ti.com/.../am57xx-ddr.dss

    Each of these scripts will generate a corresponding output file on your desktop. The first file will be useful in determining whether your issue relates to boot ROM or software. The second script will be useful for analyzing your clocks. For example, if you have not correctly enabled the I2C2 clock, we could see that in this dump. The final script is to be used in conjunction with the EMIF Tools spreadsheet to verify that you have correctly transferred the recommended settings from the spreadsheet into u-boot.

    Please zip the output of the scripts and attach to this thread.

    Best regards,
    Brad
  • 0 in reply to Brad Griffis
    Prodigy 100 points

    1. It goes high

    2.  See attached log

    3. we didn't mean too and will be addressing it on a spin,  But the result was the SD card being hooked up to 3.3v not 1.8V it should not be an issue but it could be.

    4.  SD  card primarily but we can boot from the flash software

    A. we have resolved this through help on the forum

    B. Yes we have used the EMIF tools

    C. Yes we think we think we have it right U boot no longer complains so the PMIC is on the wrong

    D. Were passed MLO and Uboot this is linux kernel boot issue

    we have not seen these scripts, we will try them. 

    Log:

    U-Boot SPL 2018.01-g131dc82830 (Mar 28 2019 - 21:38:26)
    DRA752-GP ES2.0
    Trying to boot from MMC1
    no pinctrl state for default mode
    no pinctrl state for default mode
    *** Warning - bad CRC, using default environment
    reading u-boot.img
    reading u-boot.img
    reading u-boot.img
    reading u-boot.img
    U-Boot 2018.01-g131dc82830 (Mar 28 2019 - 21:38:26 +0000)
    CPU : DRA752-GP ES2.0
    Model: TI AM5728 IDK
    Board: AM572x IDK REV
    DRAM: 2 GiB
    MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
    *** Warning - bad CRC, using default environment
    Warning: fastboot.board_rev: unknown board revision
    GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
    part_get_info_efi: *** ERROR: Invalid GPT ***
    GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
    part_get_info_efi: *** ERROR: Invalid Backup GPT ***
    SCSI: SATA link 0 timeout.
    AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
    flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
    scanning bus for devices...
    Found 0 device(s).
    Net: Could not get PHY for ethernet@48484000: addr 0
    Warning: ethernet@48484000 using MAC address from ROM
    eth0: ethernet@48484000
    Hit any key to stop autoboot: 0
    switch to partitions #0, OK
    mmc0 is current device
    SD/MMC found on device 0
    ** Unable to read file boot.scr **
    reading uEnv.txt
    574 bytes read in 4 ms (139.6 KiB/s)
    Loaded env from uEnv.txt
    Importing environment from mmc0 ...
    switch to partitions #0, OK
    mmc0 is current device
    SD/MMC found on device 0
    4547072 bytes read in 236 ms (18.4 MiB/s)
    100529 bytes read in 65 ms (1.5 MiB/s)
    ## Flattened Device Tree blob at 88000000
    Booting using the fdt blob at 0x88000000
    Loading Device Tree to 8ffe4000, end 8ffff8b0 ... OK
    Starting kernel ...
    [ 0.000000] Booting Linux on physical CPU 0x0
    [ 0.000000] Linux version 4.14.40-g4796173fc5 (cnason@hum-se-swdev) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #72 SMP PREEMPT Fri Apr 5 19:06:19 EDT 2019
    [ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
    [ 0.000000] CPU: div instructions available: patching division code
    [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [ 0.000000] OF: fdt: Machine model: TI AM5728 IDK
    [ 0.000000] using machine: Generic DRA74X (Flattened Device Tree)
    [ 0.000000] Memory policy: Data cache writealloc
    [ 0.000000] efi: Getting EFI parameters from FDT:
    [ 0.000000] efi: UEFI not found.
    [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
    [ 0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
    [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
    [ 0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
    [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
    [ 0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
    [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
    [ 0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
    [ 0.000000] cma: Reserved 24 MiB at 0x00000000fe400000
    [ 0.000000] OMAP4: Map 0x00000000ffd00000 to fe600000 for dram barrier
    [ 0.000000] DRA752 ES2.0
    [ 0.000000] start kernel 1
    [ 0.000000] start kernel 2
    [ 0.000000] percpu: Embedded 15 pages/cpu @eed34000 s31372 r8192 d21876 u61440
    [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 472640
    [ 0.000000] Kernel command line: console=ttyO2,115200n8 root=PARTUUID=687b5787-02 rw rootfstype=ext4 rootwait
    [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
    [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
    [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    [ 0.000000] Memory: 1673572K/1897472K available (10240K kernel code, 356K rwdata, 2684K rodata, 2048K init, 313K bss, 35484K reserved, 188416K cma-reserved, 1283072K highmem)
    [ 0.000000] Virtual kernel memory layout:
    [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
    [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
    [ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
    [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
    [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
    [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
    [ 0.000000] .text : 0xc0008000 - 0xc0c00000 (12256 kB)
    [ 0.000000] .init : 0xc1000000 - 0xc1200000 (2048 kB)
    [ 0.000000] .data : 0xc1200000 - 0xc12591d8 ( 357 kB)
    [ 0.000000] .bss : 0xc125b000 - 0xc12a947c ( 314 kB)
    [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
    [ 0.000000] Preemptible hierarchical RCU implementation.
    [ 0.000000] Tasks RCU enabled.
    [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
    [ 0.000000] GIC: Using split EOI/Deactivate mode
    [ 0.000000] OMAP clockevent source: timer1 at 32786 Hz
    [ 0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
    [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
    [ 0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
    [ 0.000016] Switching to timer-based delay loop, resolution 162ns
    [ 0.000340] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
    [ 0.000348] OMAP clocksource: 32k_counter at 32768 Hz
    [ 0.000791] Console: colour dummy device 80x30
    [ 0.000809] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
    [ 0.000816] This ensures that you still see kernel messages. Please
    [ 0.000823] update your kernel commandline.
    [ 0.000843] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
    [ 0.000858] pid_max: default: 32768 minimum: 301
    [ 0.000977] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [ 0.000991] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    [ 0.001523] CPU: Testing write buffer coherency: ok
    [ 0.001556] start kernel 3
    [ 0.001671] reset_init 1
    [ 0.001705] reset_init 2
    [ 0.001739] in kernel_init 1
    [ 0.001771] /cpus/cpu@0 missing clock-frequency property
    [ 0.001788] /cpus/cpu@1 missing clock-frequency property
    [ 0.001799] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [ 0.039870] Setting up static identity map for 0x80200000 - 0x80200060
    [ 0.059876] Hierarchical SRCU implementation.
    [ 0.080069] EFI services will not be available.
    [ 0.099941] smp: Bringing up secondary CPUs ...
    [ 0.170251] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [ 0.170346] smp: Brought up 1 node, 2 CPUs
    [ 0.170359] SMP: Total of 2 processors activated (24.59 BogoMIPS).
    [ 0.170367] CPU: All CPU(s) started in HYP mode.
    [ 0.170374] CPU: Virtualization extensions available.
    [ 0.170887] devtmpfs: initialized
    [ 0.170896] driver_init 1
    [ 0.170922] driver_init 2
    [ 0.170935] driver_init 3
    [ 0.171067] driver_init 4
    [ 0.171075] driver_init 5
    [ 0.187759] do_basic_setup
    [ 0.187877] do_basic_setup 2
    [ 0.187884] do_basic_setup 3
    [ 0.187893] do_basic_setup 4
    [ 0.187900] do init call level: 0
    [ 0.188000] random: get_random_u32 called from bucket_table_alloc+0x108/0x230 with crng_init=0
    [ 0.188183] do init call level: 1
    [ 0.188262] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [ 0.188449] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    [ 0.188464] futex hash table entries: 512 (order: 3, 32768 bytes)
    [ 0.192228] pinctrl core: initialized pinctrl subsystem
    [ 0.192674] DMI not present or invalid.
    [ 0.192928] NET: Registered protocol family 16
    [ 0.192963] do init call level: 2
    [ 0.193975] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [ 0.194908] omap_hwmod: l3_main_2 using broken dt data from ocp
    [ 0.330229] omap_hwmod: gpu: _wait_target_ready failed: -16
    [ 0.330257] omap_hwmod: gpu: cannot be enabled for reset (3)
    [ 0.398278] cpuidle: using governor ladder
    [ 0.398311] cpuidle: using governor menu
    [ 0.398466] do init call level: 3
    [ 0.403303] sram 40300000.ocmcram: get clock error!!!
    [ 0.406320] OMAP GPIO hardware version 0.1
    [ 0.433584] No ATAGs?
    [ 0.433654] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
    [ 0.433667] hw-breakpoint: maximum watchpoint size is 8 bytes.
    [ 0.434031] omap4_sram_init:Unable to allocate sram needed to handle errata I688
    [ 0.434042] omap4_sram_init:Unable to get sram pool needed to handle errata I688
    [ 0.434556] OMAP DMA hardware revision 0.0
    [ 0.435107] do init call level: 4
    [ 0.449495] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
    [ 0.450799] edma 43300000.edma: memcpy is disabled
    [ 0.453956] edma 43300000.edma: TI EDMA DMA engine driver
    [ 0.456635] omap-iommu 40d01000.mmu: 40d01000.mmu registered
    [ 0.456835] omap-iommu 40d02000.mmu: 40d02000.mmu registered
    [ 0.457082] omap-iommu 58882000.mmu: 58882000.mmu registered
    [ 0.457319] omap-iommu 55082000.mmu: 55082000.mmu registered
    [ 0.457660] omap-iommu 41501000.mmu: 41501000.mmu registered
    [ 0.457867] omap-iommu 41502000.mmu: 41502000.mmu registered
    [ 0.458091] iommu: Adding device 58820000.ipu to group 1
    [ 0.458165] iommu: Adding device 55020000.ipu to group 2
    [ 0.458302] iommu: Adding device 40800000.dsp to group 0
    [ 0.458532] iommu: Adding device 41000000.dsp to group 3
    [ 0.459341] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
    [ 0.459952] palmas 1-0058: Irq flag is 0x00000004
    [ 0.480525] palmas 1-0058: POLARITY_CTRL update failed: -121
    [ 0.480969] palmas: probe of 1-0058 failed with error -121
    [ 0.481178] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
    [ 0.481566] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
    [ 0.481732] media: Linux media interface: v0.10
    [ 0.481768] Linux video capture interface: v2.00
    [ 0.481844] pps_core: LinuxPPS API ver. 1 registered
    [ 0.481852] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [ 0.481871] PTP clock support registered
    [ 0.481896] EDAC MC: Ver: 3.0.0
    [ 0.482138] dmi: Firmware registration failed.
    [ 0.482266] Advanced Linux Sound Architecture Driver Initialized.
    [ 0.482837] do init call level: 5
    [ 0.482961] clocksource: Switched to clocksource arch_sys_counter
    [ 0.490521] NET: Registered protocol family 2
    [ 0.491036] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
    [ 0.491099] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
    [ 0.491225] TCP: Hash tables configured (established 8192 bind 8192)
    [ 0.491294] UDP hash table entries: 512 (order: 2, 16384 bytes)
    [ 0.491327] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
    [ 0.491448] NET: Registered protocol family 1
    [ 0.491732] RPC: Registered named UNIX socket transport module.
    [ 0.491742] RPC: Registered udp transport module.
    [ 0.491749] RPC: Registered tcp transport module.
    [ 0.491756] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [ 0.492129] do init call level: 6
    [ 0.492632] hw perfevents: no interrupt-affinity property for /pmu, guessing.
    [ 0.492802] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
    [ 0.493794] workingset: timestamp_bits=14 max_order=19 bucket_order=5
    [ 0.497823] squashfs: version 4.0 (2009/01/31) Phillip Lougher
    [ 0.498314] NFS: Registering the id_resolver key type
    [ 0.498340] Key type id_resolver registered
    [ 0.498348] Key type id_legacy registered
    [ 0.498388] ntfs: driver 2.1.32 [Flags: R/O].
    [ 0.499751] bounce: pool size: 64 pages
    [ 0.499797] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
    [ 0.499895] io scheduler noop registered
    [ 0.499905] io scheduler deadline registered
    [ 0.500058] io scheduler cfq registered (default)
    [ 0.500068] io scheduler mq-deadline registered
    [ 0.500076] io scheduler kyber registered
    [ 0.502237] phy phy-4a084000.phy.0: regulator_get phy
    [ 0.502397] phy phy-4a085000.phy.0: regulator_get phy
    [ 0.502888] phy phy-4a096000.phy.0: regulator_get phy
    [ 0.503411] phy phy-4a094000.pciephy.1: regulator_get phy
    [ 0.503706] phy phy-4a084400.phy.2: regulator_get phy
    [ 0.504628] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 ...

  • 0 in reply to chris montoya
    TI__Guru*** 125430 points
    I didn't see an attachment, just the inline paste. So does it just end suddenly with this line:

    [ 0.504628] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400

    Or maybe I'm missing the log you referenced.

    You're a lot further along than I initially realized. There's one other script you should run:

    git.ti.com/.../am57xx-padconf.dss

    It will generate an rd1 file related to the pinmuxing. I have a python script that decodes it into an easily readable format.
  • 0 in reply to Brad Griffis
    Prodigy 100 points
    No the log was what I appended.
  • 0 in reply to chris montoya
    TI__Guru*** 125430 points
    Just so we're aligned, right now I'm waiting for you to post logs from the DSS scripts. No hurry if you need more time, but I wanted to comment just in case you were waiting on something from me.
  • 0 in reply to Brad Griffis
    Prodigy 100 points

    Here are the outputs 

    am57xx-boot_2019-04-09_140942.txt

    CTRL_CORE_BOOTSTRAP = 0x00008122
    * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
    * XIP/NAND BOOTDEVICESIZE = 8-bit
    * XIP/NAND MUXCS0DEVICE = Non-muxed
    * XIP/NAND BOOTWAITEN, wait pin not monitored
    * SPEEDSELECT = 20 MHz
    * QSPI offset = 64KB
    * SD -> eMMC -> USB

    Current tracing vector, word 1 = 0x0010009b
    * Bit 0: [Boot] Passed the public reset vector
    * Bit 1: [Boot] Entered main function
    * Bit 3: [Boot] Main booting routine entered
    * Bit 4: [Memory boot] Memory booting started
    * Bit 7: [Boot] GP header found
    * Bit 20: [Boot] Configuration header found

    Current tracing vector, word 2 = 0x40001000
    * Bit 12: [Memory boot] Memory booting trial (first block)
    * Bit 30: [Boot] Jumping to Initial Software

    Current tracing vector, word 3 = 0x00000020
    * Bit 5: [Memory boot] Memory booting device SD

    Current tracing vector, word 4 = 0x00000000

    Cold reset tracing vector, word 1 = 0x0010009f
    * Bit 0: [Boot] Passed the public reset vector
    * Bit 1: [Boot] Entered main function
    * Bit 2: [Boot] Running after the cold reset
    * Bit 3: [Boot] Main booting routine entered
    * Bit 4: [Memory boot] Memory booting started
    * Bit 7: [Boot] GP header found
    * Bit 20: [Boot] Configuration header found

    Cold reset tracing vector, word 2 = 0x40001000
    * Bit 12: [Memory boot] Memory booting trial (first block)
    * Bit 30: [Boot] Jumping to Initial Software

    Cold reset tracing vector, word 3 = 0x00000020
    * Bit 5: [Memory boot] Memory booting device SD

    Cold reset tracing vector, word 4 = 0x00000000

    Current copy of the PRM_RSTST register (reset reasons) = 0x00000021
    * Bit 0 : GLOBAL_COLD_RST
    * Bit 5 : EXTERNAL_WARM_RST

    PRM_RSTST = 0x00000021
    * Bit 0 : GLOBAL_COLD_RST
    * Bit 5 : EXTERNAL_WARM_RST

    am57xx-ctt_2019-04-09_141006.rd1

    DeviceName AM572x_SR2.0_SR1.1
    0x4a005560 0x00030000
    0x4ae06118 0x00000000
    0x4a008920 0x00070000
    0x4ae06190 0x00000000
    0x4a0052e4 0x00010a04
    0x4ae061c8 0x00000000
    0x4ae06174 0x00000000
    0x4a009848 0x00000002
    0x4ae07888 0x00030000
    0x4a005228 0x00000208
    0x4a002360 0x00000000
    0x4a0051ec 0x00800501
    0x4a009770 0x00000101
    0x4a009908 0x00030000
    0x4ae07a04 0x00000001
    0x4a005254 0x00000000
    0x4ae06154 0x00000000
    0x4a009858 0x00000002
    0x4a00521c 0x00010a04
    0x4ae061bc 0x00000000
    0x4a009750 0x00030000
    0x4a009780 0x00000001
    0x4a0097a8 0x00030000
    0x4a008778 0x00030000
    0x4a009328 0x01040002
    0x4a005234 0x00000005
    0x4a005244 0x00000001
    0x4a0052b8 0x00000204
    0x4a009388 0x00040102
    0x4a005130 0x00000002
    0x4a005154 0x00000005
    0x4a0098e8 0x00030000
    0x4a008e40 0x00030000
    0x4a005550 0x00030000
    0x4a0093e8 0x00000001
    0x4ae07830 0x00000002
    0x4a00516c 0x0081f409
    0x4a009620 0x00030000
    0x4a005520 0x00070000
    0x4a005580 0x00030000
    0x4a008210 0x0000000f
    0x4a008e28 0x00030000
    0x4ae061a0 0x00000000
    0x4a009738 0x00000002
    0x4a005248 0x00000001
    0x4a009800 0x00030000
    0x4a0052c8 0x0000000a
    0x4a0052d8 0x00000005
    0x4a005140 0x0000003e
    0x4a0052e8 0x00000001
    0x4a0098a8 0x00030000
    0x4a005720 0x00070000
    0x4ae06180 0x00000000
    0x4a009798 0x00030000
    0x4ae061c0 0x00000000
    0x4a0051e0 0x00000005
    0x4ae06108 0x00000000
    0x4a0051f0 0x00000001
    0x4ae07840 0x01000002
    0x4ae06170 0x00000000
    0x4a009200 0x00000003
    0x4a0097d8 0x00030000
    0x4a005210 0x00000007
    0x4a0098f0 0x00030000
    0x4ae07838 0x00000001
    0x4a005220 0x00000202
    0x4a009868 0x00030000
    0x4a008158 0x00000003
    0x4a00519c 0x00000000
    0x4a0086a0 0x00000000
    0x4ae061d4 0x00000000
    0x4ae06138 0x00000000
    0x4ae061c4 0x00000000
    0x4a0051f4 0x00000001
    0x4ae06114 0x00000000
    0x4a008e50 0x02000001
    0x4a009760 0x00000001
    0x4a009720 0x00070000
    0x4ae061d0 0x00000000
    0x4a009878 0x00030000
    0x4a00814c 0x00006004
    0x4a008200 0x00000007
    0x4a005160 0x00000007
    0x4a0093b0 0x00070000
    0x4a005170 0x00000201
    0x4ae061d8 0x00000000
    0x4a009120 0x00070000
    0x4a008b30 0x00000001
    0x4a0052c0 0x00000228
    0x4a0051ac 0x00010a04
    0x4ae061a8 0x00000000
    0x4a00815c 0x00000004
    0x4a005568 0x00030000
    0x4a0093d0 0x08000002
    0x4a009820 0x00030000
    0x4a009220 0x00070000
    0x4a002534 0x00000000
    0x4a009020 0x00070000
    0x4a0098d0 0x00030000
    0x4a0056e0 0x00070000
    0x4a0093e0 0x00030000
    0x4a009130 0x00070000
    0x4a009850 0x00000002
    0x4a005158 0x00000004
    0x4a005764 0x00070000
    0x4a009788 0x00030000
    0x4a008160 0x0000020a
    0x4ae07878 0x00030000
    0x4a009030 0x00070000
    0x4a009890 0x00030000
    0x4a009870 0x00030000
    0x4a0097f0 0x00030000
    0x4ae06194 0x00000000
    0x4a009340 0x00070000
    0x4a0097c4 0x00030000
    0x4a009810 0x00000001
    0x4a0097b0 0x00030000
    0x4a0051dc 0x00000000
    0x4a008780 0x00030000
    0x4a005144 0x00000005
    0x4a008164 0x00000002
    0x4a008140 0x00000007
    0x4a0097c8 0x00030000
    0x4a008150 0x00000804
    0x4ae0610c 0x00000000
    0x4a0098c8 0x00030000
    0x4ae06198 0x00000000
    0x4ae06168 0x00000000
    0x4ae06184 0x00000000
    0x4ae06148 0x00000000
    0x4a0051a0 0x00000005
    0x4a0051b0 0x00000001
    0x4ae0619c 0x00000000
    0x4a0056a0 0x00070000
    0x4a009740 0x00030000
    0x4a00821c 0x00000100
    0x4a009808 0x00030000
    0x4a009728 0x00030000
    0x4a005290 0x00000000
    0x4ae061cc 0x00000000
    0x4a005558 0x00030000
    0x4ae0612c 0x00000000
    0x4ae06178 0x00000000
    0x4a005620 0x00070000
    0x4a009830 0x00030000
    0x4a00818c 0x0401e009
    0x4a00820c 0x04004b00
    0x4a008f28 0x00030000
    0x4a002544 0xf757fdc0
    0x4a009898 0x00030000
    0x4ae061b0 0x00000000
    0x4a009840 0x00000002
    0x4a009768 0x00000001
    0x4a009904 0x00030000
    0x4a00515c 0x00000006
    0x4ae061b8 0x00000000
    0x4a0052bc 0x0000000a
    0x4a0093b8 0x00070000
    0x4a008b38 0x00000001
    0x4ae061b4 0x00000000
    0x4a009778 0x00000001
    0x4a005570 0x00030000
    0x4a0097a0 0x00000002
    0x4a0052a4 0x00000000
    0x4a005660 0x00070000
    0x4ae06110 0x00000002
    0x4a009828 0x00030000
    0x4ae06164 0x00000000
    0x4a008b40 0x00000000
    0x4ae06160 0x00000000
    0x4ae0615c 0x00000000
    0x4ae06158 0x00000000
    0x4a009028 0x00070000
    0x4a0098e0 0x00030000
    0x4a005284 0x00000005
    0x4a005294 0x00000001
    0x4a009330 0x01040002
    0x4ae0614c 0x00000000
    0x4a005420 0x00070000
    0x4a0093f0 0x00070000
    0x4ae06150 0x00000000
    0x4a008180 0x00000007
    0x4a0052b4 0x0000fa04
    0x4a008190 0x00000002
    0x4a00512c 0x00010a04
    0x4a005100 0x00000110
    0x4a0097f8 0x00030000
    0x4a008f20 0x00070000
    0x4ae0618c 0x00000000
    0x4a0098a0 0x00030000
    0x4ae061e0 0x00000000
    0x4a0098c0 0x00030000
    0x4a009790 0x00030000
    0x4a009838 0x01000002
    0x4a009818 0x00000001
    0x4a0097b8 0x00030000
    0x4a008728 0x00000001
    0x4a0097d0 0x00030000
    0x4a008e20 0x00030000
    0x4a0098f8 0x00030000
    0x4ae07880 0x00030000
    0x4ae0616c 0x00000000
    0x4a009860 0x00030000
    0x4ae061ac 0x00000000
    0x4a0098b0 0x00030000
    0x4a0052c4 0x00000208
    0x4a00513c 0x00000204
    0x4ae06120 0x00000000
    0x4a009748 0x00030000
    0x4ae06144 0x00000000
    0x4a005578 0x00030000
    0x4a005240 0x00004b01
    0x4a009718 0x00070000
    0x4a009730 0x00030000
    0x4a0052a8 0x00000007
    0x4a005120 0x00000007
    0x4a0086b0 0x00000000
    0x4ae06188 0x00000000
    0x4ae061a4 0x00000000
    0x4ae06128 0x00000000

    am57xx-ddr_2019-04-09_141018.txt

    ********************** DPLL_DDR **********************

    CTRL_CORE_BOOTSTRAP = 0x00008122
    * SPEEDSELECT = 20 MHz
    CM_CLKSEL_DPLL_DDR = 0x00010a04
    * DPLL_MULT = 266 (x266)
    * DPLL_DIV = 4 (/5)
    CM_DIV_M2_DPLL_DDR = 0x00000202
    * CLKST = 1: M2 output clock enabled
    * DIVHS = 2 (/2)
    CM_DIV_H11_DPLL_DDR = 0x00000208
    * CLKST = 1: H11 output clock enabled
    * DIVHS = 8 (/8)

    DPLL_DDR Summary
    -> F_input = 20 MHz
    -> F_dpll_ddr = 2128 MHz
    -> CLKOUT_M2 = EMIF_PHY_GCLK = 532 MHz
    -> CLKOUTX2_H11 = EMIF_DLL_GCLK = 266 MHz

    ********************** DMM - LISA **********************

    DMM_LISA_MAP_0 = 0x00000000
    DMM_LISA_MAP_1 = 0x00000000
    DMM_LISA_MAP_2 = 0x00000000
    DMM_LISA_MAP_3 = 0x80740300
    * System Address Mapping = 0x80000000
    * Section Size = 2048 MB
    * Mapped to EMIF1 and EMIF2: 128-byte interleaving

    ********************** EMIF1 **********************

    CTRL_CORE_CONTROL_DDRCACH1_0 = 0x80808080
    ddr1_casn, ddr1_rasn, ddr1_rst, ddr1_wen, ddr1_csn[0], ddr1_cke, ddr1_odt[0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms
    ddr1_a[15:0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms
    ddr1_ba[0], ddr1_ba[1], ddr1_ba[2]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms
    ddr1_ck, ddr1_nck
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms

    CTRL_CORE_CONTROL_DDRCH1_0 = 0x40404040
    ddr1_d[7:0], ddr1_dqm[0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr1_dqs[0], ddr1_dqsn[0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr1_d[15:8], ddr1_dqm[1]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr1_dqs[1], ddr1_dqsn[1]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms

    CTRL_CORE_CONTROL_DDRCH1_1 = 0x40404040
    ddr1_d[23:16], ddr1_dqm[2]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr1_dqs[2], ddr1_dqsn[2]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr1_d[31:24], ddr1_dqm[3]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr1_dqs[3], ddr1_dqsn[3]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms

    CTRL_CORE_CONTROL_DDRCH1_2 = 0x00404000
    ddr1_ecc_d[7:0], ddr1_dqm_ecc
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr1_dqs_ecc, ddr1_dqsn_ecc
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms

    CTRL_CORE_CONTROL_DDRIO_0 = 0x00094a40
    ddr1_d[7:0], ddr1_d[15:8]
    * Internal VREF disabled
    ddr1_d[23:16], ddr1_d[31:24], ddr1_ecc_d[7:0]
    * Internal VREF disabled

    CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT = 0x0001c1a7
    EMIF_STATUS = 0x40000004

    EMIF_SDRAM_CONFIG = 0x61851b32
    EMIF_SDRAM_CONFIG_2 = 0x08000000
    EMIF_SDRAM_REFRESH_CONTROL = 0x00001035
    EMIF_SDRAM_TIMING_1 = 0xcccf36ab
    EMIF_SDRAM_TIMING_2 = 0x308f7fda
    EMIF_SDRAM_TIMING_3 = 0x409f88a8
    EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
    EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
    EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
    EMIF_DDR_PHY_CONTROL_1 = 0x0e24400b
    * Bits 4:0 READ_LATENCY = 11
    * Bit 9 PHY_FAST_DLL_LOCK = 0
    * Bits 17:10 PHY_DLL_LOCK_DIFF = 16
    * Bit 18 PHY_INVERT_CLKOUT = 1
    * Bit 19 PHY_DIS_CALIB_RST = 0
    * Bit 20 PHY_CLK_STALL_LEVEL = 0
    * Bit 21 PHY_HALF_DELAYS = 1
    * Bit 25 WRLVL_MASK = 1
    * Bit 26 RDLVLGATE_MASK = 1
    * Bit 27 RDLVL_MASK = 1

    EMIF_EXT_PHY_CONTROL_1 = 0x10040100
    EMIF_EXT_PHY_CONTROL_2 = 0x07000087
    EMIF_EXT_PHY_CONTROL_3 = 0x07000086
    EMIF_EXT_PHY_CONTROL_4 = 0x07000077
    EMIF_EXT_PHY_CONTROL_5 = 0x07000070
    EMIF_EXT_PHY_CONTROL_6 = 0x07000000
    EMIF_EXT_PHY_CONTROL_7 = 0x00000041
    EMIF_EXT_PHY_CONTROL_8 = 0x0000003f
    EMIF_EXT_PHY_CONTROL_9 = 0x0000003e
    EMIF_EXT_PHY_CONTROL_10 = 0x0000003a
    EMIF_EXT_PHY_CONTROL_11 = 0x0000007f
    EMIF_EXT_PHY_CONTROL_12 = 0x0077006b
    EMIF_EXT_PHY_CONTROL_13 = 0x01a70066
    EMIF_EXT_PHY_CONTROL_14 = 0x00070062
    EMIF_EXT_PHY_CONTROL_15 = 0x00a60061
    EMIF_EXT_PHY_CONTROL_16 = 0x02d00020
    EMIF_EXT_PHY_CONTROL_17 = 0x0057004b
    EMIF_EXT_PHY_CONTROL_18 = 0x01870046
    EMIF_EXT_PHY_CONTROL_19 = 0x03e70042
    EMIF_EXT_PHY_CONTROL_20 = 0x00860041
    EMIF_EXT_PHY_CONTROL_21 = 0x02b00000
    EMIF_EXT_PHY_CONTROL_22 = 0x00000000
    EMIF_EXT_PHY_CONTROL_23 = 0x00600020
    EMIF_EXT_PHY_CONTROL_24 = 0x40011080
    EMIF_EXT_PHY_CONTROL_25 = 0x08102040
    EMIF_EXT_PHY_CONTROL_26 = 0x00000000
    EMIF_EXT_PHY_CONTROL_27 = 0x00000000
    EMIF_EXT_PHY_CONTROL_28 = 0x00000000
    EMIF_EXT_PHY_CONTROL_29 = 0x00000000
    EMIF_EXT_PHY_CONTROL_30 = 0x00000000
    EMIF_EXT_PHY_CONTROL_31 = 0x00000000
    EMIF_EXT_PHY_CONTROL_32 = 0x00000000
    EMIF_EXT_PHY_CONTROL_33 = 0x00000000
    EMIF_EXT_PHY_CONTROL_34 = 0x00000000
    EMIF_EXT_PHY_CONTROL_35 = 0x00000000
    EMIF_EXT_PHY_CONTROL_36 = 0x00000177

    EMIF_EXT_PHY_STATUS_1 = 0x001141f3
    EMIF_EXT_PHY_STATUS_2 = 0xa4463313
    EMIF_EXT_PHY_STATUS_3 = 0x6db610d8
    EMIF_EXT_PHY_STATUS_4 = 0x00020000
    EMIF_EXT_PHY_STATUS_5 = 0x00099999
    EMIF_EXT_PHY_STATUS_6 = 0x00002924
    EMIF_EXT_PHY_STATUS_7 = 0x00000041
    EMIF_EXT_PHY_STATUS_8 = 0x0000003f
    EMIF_EXT_PHY_STATUS_9 = 0x0000003e
    EMIF_EXT_PHY_STATUS_10 = 0x0000003a
    EMIF_EXT_PHY_STATUS_11 = 0x0000007f
    EMIF_EXT_PHY_STATUS_12 = 0x07000087
    EMIF_EXT_PHY_STATUS_13 = 0x07000086
    EMIF_EXT_PHY_STATUS_14 = 0x07000077
    EMIF_EXT_PHY_STATUS_15 = 0x07000070
    EMIF_EXT_PHY_STATUS_16 = 0x07000000
    EMIF_EXT_PHY_STATUS_17 = 0x0077006b
    EMIF_EXT_PHY_STATUS_18 = 0x01a70066
    EMIF_EXT_PHY_STATUS_19 = 0x01870046
    EMIF_EXT_PHY_STATUS_20 = 0x00a60061
    EMIF_EXT_PHY_STATUS_21 = 0x02d00020
    EMIF_EXT_PHY_STATUS_22 = 0x0057004b
    EMIF_EXT_PHY_STATUS_23 = 0x01870046
    EMIF_EXT_PHY_STATUS_24 = 0x03e70042
    EMIF_EXT_PHY_STATUS_25 = 0x00860041
    EMIF_EXT_PHY_STATUS_26 = 0x02b00000
    EMIF_EXT_PHY_STATUS_27 = 0x11ff1111
    EMIF_EXT_PHY_STATUS_28 = 0x00000000

    ********************** EMIF2 **********************

    CTRL_CORE_CONTROL_DDRCACH2_0 = 0x80808080
    ddr2_casn, ddr2_rasn, ddr2_rst, ddr2_wen, ddr2_csn[0], ddr2_cke, ddr2_odt[0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms
    ddr2_a[15:0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms
    ddr2_ba[0], ddr2_ba[1], ddr2_ba[2]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms
    ddr2_ck, ddr2_nck
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 34 Ohms

    CTRL_CORE_CONTROL_DDRCH2_0 = 0x40404040
    ddr2_d[7:0], ddr2_dqm[0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr2_dqs[0], ddr2_dqsn[0]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr2_d[15:8], ddr2_dqm[1]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr2_dqs[1], ddr2_dqsn[1]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms

    CTRL_CORE_CONTROL_DDRCH2_1 = 0x40404040
    ddr2_d[23:16], ddr2_dqm[2]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr2_dqs[2], ddr2_dqsn[2]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr2_d[31:24], ddr2_dqm[3]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms
    ddr2_dqs[3], ddr2_dqsn[3]
    * Pull logic is disabled
    * Slew rate is 0, where 0=fastest and 7=slowest
    * Output Impedance = 48 Ohms

    CTRL_CORE_CONTROL_DDRIO_1 = 0x04a52000
    ddr2_d[7:0], ddr2_d[15:8]
    * Internal VREF disabled
    ddr2_d[23:16], ddr2_d[31:24]
    * Internal VREF disabled

    CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT = 0x0001c1a7
    EMIF_STATUS = 0x40000004

    EMIF_SDRAM_CONFIG = 0x61851b32
    EMIF_SDRAM_CONFIG_2 = 0x08000000
    EMIF_SDRAM_REFRESH_CONTROL = 0x00001035
    EMIF_SDRAM_TIMING_1 = 0xcccf36b3
    EMIF_SDRAM_TIMING_2 = 0x308f7fda
    EMIF_SDRAM_TIMING_3 = 0x407f88a8
    EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
    EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
    EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
    EMIF_DDR_PHY_CONTROL_1 = 0x0e24400b
    * Bits 4:0 READ_LATENCY = 11
    * Bit 9 PHY_FAST_DLL_LOCK = 0
    * Bits 17:10 PHY_DLL_LOCK_DIFF = 16
    * Bit 18 PHY_INVERT_CLKOUT = 1
    * Bit 19 PHY_DIS_CALIB_RST = 0
    * Bit 20 PHY_CLK_STALL_LEVEL = 0
    * Bit 21 PHY_HALF_DELAYS = 1
    * Bit 25 WRLVL_MASK = 1
    * Bit 26 RDLVLGATE_MASK = 1
    * Bit 27 RDLVL_MASK = 1

    EMIF_EXT_PHY_CONTROL_1 = 0x10040100
    EMIF_EXT_PHY_CONTROL_2 = 0x0700008e
    EMIF_EXT_PHY_CONTROL_3 = 0x0700008e
    EMIF_EXT_PHY_CONTROL_4 = 0x0700007f
    EMIF_EXT_PHY_CONTROL_5 = 0x07000079
    EMIF_EXT_PHY_CONTROL_6 = 0x00000000
    EMIF_EXT_PHY_CONTROL_7 = 0x0000003c
    EMIF_EXT_PHY_CONTROL_8 = 0x00000038
    EMIF_EXT_PHY_CONTROL_9 = 0x00000039
    EMIF_EXT_PHY_CONTROL_10 = 0x0000003a
    EMIF_EXT_PHY_CONTROL_11 = 0x00000000
    EMIF_EXT_PHY_CONTROL_12 = 0x024d0077
    EMIF_EXT_PHY_CONTROL_13 = 0x0010007b
    EMIF_EXT_PHY_CONTROL_14 = 0x02bb006f
    EMIF_EXT_PHY_CONTROL_15 = 0x039d006e
    EMIF_EXT_PHY_CONTROL_16 = 0x00000000
    EMIF_EXT_PHY_CONTROL_17 = 0x022d0057
    EMIF_EXT_PHY_CONTROL_18 = 0x03f0005b
    EMIF_EXT_PHY_CONTROL_19 = 0x029b004f
    EMIF_EXT_PHY_CONTROL_20 = 0x037d004e
    EMIF_EXT_PHY_CONTROL_21 = 0x00000000
    EMIF_EXT_PHY_CONTROL_22 = 0x00000000
    EMIF_EXT_PHY_CONTROL_23 = 0x00600020
    EMIF_EXT_PHY_CONTROL_24 = 0x40011080
    EMIF_EXT_PHY_CONTROL_25 = 0x08102040
    EMIF_EXT_PHY_CONTROL_26 = 0x00000000
    EMIF_EXT_PHY_CONTROL_27 = 0x00000000
    EMIF_EXT_PHY_CONTROL_28 = 0x00000000
    EMIF_EXT_PHY_CONTROL_29 = 0x00000000
    EMIF_EXT_PHY_CONTROL_30 = 0x00000000
    EMIF_EXT_PHY_CONTROL_31 = 0x00000000
    EMIF_EXT_PHY_CONTROL_32 = 0x00000000
    EMIF_EXT_PHY_CONTROL_33 = 0x00000000
    EMIF_EXT_PHY_CONTROL_34 = 0x00000000
    EMIF_EXT_PHY_CONTROL_35 = 0x00000000
    EMIF_EXT_PHY_CONTROL_36 = 0x00000177

    EMIF_EXT_PHY_STATUS_1 = 0x0010e1f3
    EMIF_EXT_PHY_STATUS_2 = 0x7c422516
    EMIF_EXT_PHY_STATUS_3 = 0x0db60008
    EMIF_EXT_PHY_STATUS_4 = 0x00020000
    EMIF_EXT_PHY_STATUS_5 = 0x00009999
    EMIF_EXT_PHY_STATUS_6 = 0x00000924
    EMIF_EXT_PHY_STATUS_7 = 0x0000003c
    EMIF_EXT_PHY_STATUS_8 = 0x00000038
    EMIF_EXT_PHY_STATUS_9 = 0x00000039
    EMIF_EXT_PHY_STATUS_10 = 0x0000003a
    EMIF_EXT_PHY_STATUS_11 = 0x00000000
    EMIF_EXT_PHY_STATUS_12 = 0x0700008e
    EMIF_EXT_PHY_STATUS_13 = 0x0700008e
    EMIF_EXT_PHY_STATUS_14 = 0x0700007f
    EMIF_EXT_PHY_STATUS_15 = 0x07000079
    EMIF_EXT_PHY_STATUS_16 = 0x00000000
    EMIF_EXT_PHY_STATUS_17 = 0x024d0077
    EMIF_EXT_PHY_STATUS_18 = 0x0010007b
    EMIF_EXT_PHY_STATUS_19 = 0x03f0005b
    EMIF_EXT_PHY_STATUS_20 = 0x039d006e
    EMIF_EXT_PHY_STATUS_21 = 0x00000000
    EMIF_EXT_PHY_STATUS_22 = 0x022d0057
    EMIF_EXT_PHY_STATUS_23 = 0x03f0005b
    EMIF_EXT_PHY_STATUS_24 = 0x029b004f
    EMIF_EXT_PHY_STATUS_25 = 0x037d004e
    EMIF_EXT_PHY_STATUS_26 = 0x00000000
    EMIF_EXT_PHY_STATUS_27 = 0x10f01111
    EMIF_EXT_PHY_STATUS_28 = 0x00000000

    am57xx-padconf_2019-04-09_141044.rd1

    PadConf AM572x_SR2.0_SR1.1
    0x4a003400 0x0005000f
    0x4a003404 0x0005000f
    0x4a003408 0x0005000f
    0x4a00340c 0x0005000f
    0x4a003410 0x0005000f
    0x4a003414 0x0005000f
    0x4a003418 0x0005000f
    0x4a00341c 0x0005000f
    0x4a003420 0x0005000f
    0x4a003424 0x0005000f
    0x4a003428 0x0005000f
    0x4a00342c 0x0005000f
    0x4a003430 0x0005000f
    0x4a003434 0x0005000f
    0x4a003438 0x0005000f
    0x4a00343c 0x0005000f
    0x4a003440 0x00050106
    0x4a003444 0x00050106
    0x4a003448 0x00050106
    0x4a00344c 0x00050106
    0x4a003450 0x00050106
    0x4a003454 0x00050106
    0x4a003458 0x00050106
    0x4a00345c 0x00050106
    0x4a003460 0x00050106
    0x4a003464 0x00050106
    0x4a003468 0x00050106
    0x4a00346c 0x00050106
    0x4a003470 0x00050106
    0x4a003474 0x00050101
    0x4a003478 0x00050101
    0x4a00347c 0x00050101
    0x4a003480 0x00050101
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  • 0 in reply to chris montoya
    TI__Guru*** 125430 points
    Please zip them and attach the zip file. It's much easier for me to use.
  • 0 in reply to chris montoya
    TI__Guru*** 125430 points
    From the boot output, I see that you have a warm reset latched. That means you likely have not properly implemented the workaround to errata i727 and i729. Please see the errata for more details. That's likely unrelated to this issue, but something you should fix to improve your overall design robustness.

    From the padconf output, I see you have multiple pins muxed to UART3:

    CTRL_CORE_PAD_UART3_RXD 0x4A003648 (uart3_rxd)
    CTRL_CORE_PAD_UART2_CTSN 0x4A0037F8 (uart3_rxd)
    CTRL_CORE_PAD_UART3_TXD 0x4A00364C (uart3_txd)
    CTRL_CORE_PAD_UART2_RTSN 0x4A0037FC (uart3_txd)

    This could be the reason why you suddenly stop seeing the console when it gets to the line about pinmux. Also, the slew rates are not correct for these pins, i.e. the default value is not being left intact. So somewhere you have an issue with how you're configuring the pin muxing. For the AM57xx, the pin muxing should all be specified in u-boot in the mux_data.h file. You are intended to generate that data first by using the PinMux Tool, and then by downloading the data from the PinMux tool and converting it to a C structure using the supplied Perl script. That process is discussed in greater detail in the IODELAY app note:

    www.ti.com/.../sprac44

    For the EMIF configuration, do you have a filled out EMIF spreadsheet that you can attach? I'd like to compare the txt files against that to see how things look.
  • 0 in reply to Brad Griffis
    TI__Guru*** 125430 points

    Hi Chris,

    Any updates? I hope the pinmux change did the trick!

    Best regards,

    Brad

  • 0 in reply to Brad Griffis
    Prodigy 100 points

    We resolved the issue it turned out to be related to the mapping of the PMIC. 

  • 0 in reply to chris montoya
    TI__Guru*** 125430 points

    That's great news!  Thanks for the update.  Please click "verified" on your previous reply to close out this thread.