Linux/AM3359: Issue in loading U-boot-SPL

sandeep motupalli

Part Number: AM3359
Other Parts Discussed in Thread: AM3358

Tool/software: Linux

We have a custom board based on TI’s Sitara AM3359 ICE V2 and we are trying to bring up the board in UART boot mode.

We are getting the “CCCC…” Prints on Uart 0 from the processor. When we try to load the “u-boot-spl.bin” file through x-modem from Uart, It shows the data transfer is successful. But we are not getting any prints of SPL after it is loaded (we have enabled “#define DEBUG” in the am335x_evm.h file). When we try to load the “u-boot.img” file through y-modem afterwards, we get “Transfer incomplete” message.

We have done the DDR initialization as per TI’s Guidelines using the Ratio-seed and DDR timing calculation .xlxs spread sheets provided by TI. We have modified the values in the GEL file by the values we got from the spread sheets and tested the DDR using JTAG and CCS8. DDR tests pass and We are able to read and write to the DDR location through memory browser from the CCS IDE. We have used the same values in the “ddr_defs.h” file and built the spl and u-boot files. Our DDR is the same as the one used in the Sitar am3359 ICE v2 board.

I am attaching the Spread sheets and the GEL files along with the ddr_defs.h file used for building u-boot and u-boot-spl. Kindly help me in solving this issue as soon as possible.3240.AM335x_DDR_register_calc_tool.xls 6472.ddr_defs.h AM3358_StarterKit_APR.gel 3240.AM335x_DDR_register_calc_tool.xls

over 6 years ago

0 Kemal R. Shakir over 6 years ago

TI__Guru 55345 points

Hello sandeep,

Can you also run the DDR diagnostic scripts from this post and make sure that you are loading the u-boot.img by ymodem protocol in 1k mode and pass -v argument to sx to get a more verbose output?
Also please, pay attention on that the console in AM3359 ICE V2 is changed to UART3 by this line stdout-path = &uart3; in <Processor SDK>/board-support/u-boot-<version>/arch/arm/dts/am335x-icev2.dts for U-Boot and by this init_console environment veriable in <Processor SDK>/board-support/u-boot-<version>/include/configs/am335x_evm.h for kernel.

Best regards,
Kemal

0 Chinmay Pramod over 6 years ago in reply to Kemal R. Shakir

Intellectual 460 points

Hi Kemal,

Sorry for the late reply. We have run the DDR diagnostic scripts.

I am attaching the output txt file.

Fullscreen MGCM-am335x-ddr-analysis_2019-04-23_162624.txt Download

EMIF: SDRAM_CONFIG = 0x4104bab2
  * Bits 26:24 (reg_ddr_term) set for 75 Ohm (001b)
  * Bits 19:18 (reg_sdram_drive) set for weak drive (01b)
EMIF: PWR_MGMT_CTRL = 0x00000000
 * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit
 * Please see the silicon errata for more details.
DDR PHY: DDR_PHY_CTRL_1 = 0x00000000
  * WARNING: reg_phy_enable_dynamic_pwrdn disabled.
  * Bits 9:8 (reg_phy_rd_local_odt) configured as no termination (00b)

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000000
*(0x4c000008) = 0x4104bab2
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x80001388
*(0x4c000014) = 0x00001388
*(0x4c000018) = 0x08891599
*(0x4c00001c) = 0x08891599
*(0x4c000020) = 0x148b31ca
*(0x4c000024) = 0x148b31ca
*(0x4c000028) = 0x00ffe82f
*(0x4c00002c) = 0x00ffe82f
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffffff
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x00000000
*(0x4c000084) = 0x00000000
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0x17351a48
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x00000000
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00000000
*(0x4c0000e8) = 0x00000000
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x00000004
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_CMD1_IOCTRL = 0x00000004
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_CMD2_IOCTRL = 0x00000004
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_DATA0_IOCTRL = 0x00000004
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_DATA1_IOCTRL = 0x00000004
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew fastest
    - Drive Strength 5 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew fastest
    - Drive Strength 9 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00010107
  * VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000000
  * CKE gated (forces pin low).

Also attaching am335x-icev2.dts file:

Fullscreen U-boot DTS - am335x-icev2.txt Download

/*
 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * AM335x ICE V2 board
 * http://www.ti.com/tool/tmdsice3359
 */

/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "TI AM3359 ICE-V2";
	compatible = "ti,am3359-icev2", "ti,am33xx";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	chosen {
		stdout-path = &uart0;
	};

	vbat: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};

	vtt_fixed: fixedregulator1 {
		compatible = "regulator-fixed";
		regulator-name = "vtt";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;
		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
	};

	leds-iio {
		status = "disabled";
		compatible = "gpio-leds";
		led-out0 {
			label = "out0";
			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out1 {
			label = "out1";
			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out2 {
			label = "out2";
			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out3 {
			label = "out3";
			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out4 {
			label = "out4";
			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out5 {
			label = "out5";
			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out6 {
			label = "out6";
			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out7 {
			label = "out7";
			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	/* Tricolor status LEDs */

	gpio-decoder {
		compatible = "gpio-decoder";
		gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
			<&pca9536 2 GPIO_ACTIVE_HIGH>,
			<&pca9536 1 GPIO_ACTIVE_HIGH>,
			<&pca9536 0 GPIO_ACTIVE_HIGH>;
		linux,axis = <0>; /* ABS_X */
		decoder-max-value = <9>;
	};
};

&am33xx_pinmux {


	 gpio0_pins_default: gpio0_pins_default {
                pinctrl-single,pins = <
                      AM33XX_IOPAD(0x944, PIN_INPUT | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] */
                >;
        };

        gpio1_pins_default: gpio1_pins_default {
                pinctrl-single,pins = <
                      AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)/* (T15) M1 gpmc_a7.gpio1[23] */
                      AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (V16) M2 gpmc_a8.gpio1[24] */
                      AM33XX_IOPAD(0x868, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */
                >;
        };
        gpio2_pins_default: gpio2_pins_default {
                pinctrl-single,pins = <
                        AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (R6) M0 lcd_ac_bias_en.gpio2[25] */
                >;
        };


	i2c0_pins_default: i2c0_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
		>;
	};

	spi0_pins_default: spi0_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */
			AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
		>;
	};
	
	spi1_pins_default: spi1_pins_default {
                pinctrl-single,pins = <
                AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE3) /* (A13) mcasp0_aclkx.spi1_sclk */
                AM33XX_IOPAD(0x994, PIN_INPUT_PULLUP | MUX_MODE3)/* (B13) mcasp0_fsx.spi1_d0 */
                AM33XX_IOPAD(0x998, PIN_INPUT_PULLUP | MUX_MODE3) /* (D12) mcasp0_axr0.spi1_d1 */
                AM33XX_IOPAD(0x99c, PIN_INPUT_PULLUP | MUX_MODE3) /* (C12) mcasp0_ahclkr.spi1_cs0 */
                >;
        };


	uart3_pins_default: uart3_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
			AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
		>;
	};
	
	 uart4_pins_default: uart4_pins_default {
                pinctrl-single,pins = <
                        AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */
                        AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */
                >;
        };

     cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                                /* Slave 1 */
                AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_tctl */
                AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rctl */
                AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
                AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
                AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
                AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)/* mii1_txd0.rgmii1_td0 */

                AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rgmii1_tclk */
                AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rgmii1_rclk */
                AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
                AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
                AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
                AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
                AM33XX_IOPAD(0xA34, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (F15) USB1_DRVVBUS.gpio3[13] */
        >;
        };

        cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J16) gmii1_txen.rgmii1_tctl */
                AM33XX_IOPAD(0x918, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J17) gmii1_rxdv.rgmii1_rctl */
                AM33XX_IOPAD(0x92c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K18) gmii1_txclk.rgmii1_tclk */
                AM33XX_IOPAD(0x930, (PIN_INPUT_PULLDOWN | MUX_MODE7)) /* (L18) gmii1_rxclk.rgmii1_rclk */
                AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K17) gmii1_txd0.rgmii1_td0 */
                AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K16) gmii1_txd1.rgmii1_td1 */
                AM33XX_IOPAD(0x920, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (K15) gmii1_txd2.rgmii1_td2 */
                AM33XX_IOPAD(0x91c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (J18) gmii1_txd3.rgmii1_td3 */
                AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (M16) gmii1_rxd0.rgmii1_rd0 */
                AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L15) gmii1_rxd1.rgmii1_rd1 */
                AM33XX_IOPAD(0x938, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L16) gmii1_rxd2.rgmii1_rd2 */
                AM33XX_IOPAD(0x934, (PIN_INPUT_PULLDOWN | MUX_MODE7) ) /* (L17) gmii1_rxd3.rgmii1_rd3 */
                AM33XX_IOPAD(0xA34, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    

                >;
        };

        davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                        /* MDIO */
                        AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))     /* mdio_data.mdio_data */
                        AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))                    /* mdio_clk.mdio_clk */
        
                >;
        };

        davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                        /* MDIO reset value */
                        AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
                        AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
                >;
        };


};

&gpio0 {
        /* Do not idle the GPIO used for holding the VTT regulator */
        ti,no-reset-on-init;
        ti,no-idle-on-init;
        pinctrl-names = "default";
        pinctrl-0 = <&gpio0_pins_default>;
	status = "okay";
};

&gpio1 {
        /* Do not idle the GPIO used for holding the VTT regulator */
        ti,no-reset-on-init;
        ti,no-idle-on-init;
        pinctrl-names = "default";
        pinctrl-0 = <&gpio1_pins_default>;
        status = "okay";
};

&gpio2 {
        /* Do not idle the GPIO used for holding the VTT regulator */
        ti,no-reset-on-init;
        ti,no-idle-on-init;
        pinctrl-names = "default";
        pinctrl-0 = <&gpio2_pins_default>;
        status = "okay";
};


&mac {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&cpsw_default>;
    pinctrl-1 = <&cpsw_sleep>;
    status = "okay";
};

&davinci_mdio {
    pinctrl-names = "default", "sleep";
    compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
    pinctrl-0 = <&davinci_mdio_default>;
    pinctrl-1 = <&davinci_mdio_sleep>;
    status = "okay";

    dp83867_0: ethernet-phy@0 {
        reg = <0>;
        ti,rx-internal-delay = <DP83867_RGMIIDCTL_4_00_NS>;
        ti,tx-internal-delay = <DP83867_RGMIIDCTL_4_00_NS>;
        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
        ti,min-output-impedance;
        ti,dp83867-rxctrl-strap-quirk;
    };

};

&cpsw_emac0 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "rgmii-id";
};


&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins_default>;

	status = "okay";
	clock-frequency = <400000>;

	tps: power-controller@2d {
		reg = <0x2d>;
	};

	tpic2810: gpio@60 {
		compatible = "ti,tpic2810";
		reg = <0x60>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9536: gpio@41 {
		compatible = "ti,pca9536";
		reg = <0x41>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};
&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins_default>;
	status = "okay";

	sn65hvs882@1 {
		compatible = "pisosr-gpio";
		gpio-controller;
		#gpio-cells = <2>;

		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;

		reg = <1>;
		spi-max-frequency = <1000000>;
		spi-cpol;
	};

	spi_nor: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "winbond,w25q64", "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		m25p,fast-read;
		reg = <0>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@1 {
			label = "u-boot";
			reg = <0x80000 0x100000>;
			read-only;
		};

		partition@2 {
			label = "u-boot-env";
			reg = <0x180000 0x20000>;
			read-only;
		};

		partition@3 {
			label = "misc";
			reg = <0x1A0000 0x660000>;
		};
	};

};
&spi1 {
	#address-cells = <1>;
	#size-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins_default>;
	ti,pindir-d0-out-d1-in = <1>;
	status = "okay";
	channel@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "mt25ql02g";
		spi-max-frequency = <500000>;
	/*	m25p,fast-read;*/
		reg = <0>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@1 {
			label = "u-boot";
			reg = <0x80000 0x100000>;
			read-only;
		};

		partition@2 {
			label = "u-boot-env";
			reg = <0x180000 0x20000>;
			read-only;
		};

		partition@3 {
			label = "misc";
			reg = <0x1A0000 0x660000>;
		};
	};

};


&tscadc {
	status = "okay";
	adc {
		ti,adc-channels = <1 2 3 4 5 6 7>;
	};
};

#include "tps65910.dtsi"

&tps {
	vcc1-supply = <&vbat>;
	vcc2-supply = <&vbat>;
	vcc3-supply = <&vbat>;
	vcc4-supply = <&vbat>;
	vcc5-supply = <&vbat>;
	vcc6-supply = <&vbat>;
	vcc7-supply = <&vbat>;
	vccio-supply = <&vbat>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1326000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1144000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-always-on;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&gpio0 {
	/* Do not idle the GPIO used for holding the VTT regulator */
	ti,no-reset-on-init;
	ti,no-idle-on-init;

	p7 {
		gpio-hog;
		gpios = <7 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "FET_SWITCH_CTRL";
	};
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins_default>;
	status = "okay";
};
&uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins_default>;
        status = "okay";
};

&gpio3 {
	p4 {
		gpio-hog;
		gpios = <4 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "PR1_MII_CTRL";
	};

	p10 {
		gpio-hog;
		gpios = <10 GPIO_ACTIVE_HIGH>;
		/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
		output-high;
		line-name = "MUX_MII_CTL1";
	};
};

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	dual_emac = <1>;
	mode-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};



&davinci_mdio {
	pinctrl-names = "default", "sleep";
	compatible = "ti, cpsw-mdio","ti,davinci_mdio";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";
	ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
	ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	ti,min-output-impedance;
	ti,dp83867-rxctrl-strap-quirk;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <0x0>;
	phy-mode = "rgmii-id";
	status = "okay";
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <0x0>;
	phy-mode = "rgmii-id";
	status = "okay";
};


&i2c1{
        compatible = "ti,omap4-i2c";
        #address-cells = <1>;
        #size-cells = <0>;
        ti,hwmods = "i2c2";
        reg = <0x4802a000 0x1000>;
        interrupts = <71>;
        status = "okay";
		ad7414@48 {
			compatible = "analog,ad7414";
        		reg = <0x48>;
      		  	status = "okay";
    			};
      };


&gpmc {
status = "okay";
pinctrl-names = "default";
/*pinctrl-0 = <&gpmc_pins>;*/
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000C0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001C0000 0x00020000>;
};
partition@7 {
label = "NAND.kernel-dtb";
reg = <0x001E0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x0F600000>;
};
};

fpga{
reg = <1 0 0x01000000>; /*CSn1*/

bank-width = <2>; /* GPMC_CONFIG1_DEVICESIZE(1) */

/*gpmc,burst-write;*/
/*gpmc,burst-read;*/
/*gpmc,burst-wrap;*/
gpmc,sync-read; /* GPMC_CONFIG1_READTYPE_ASYNC */
gpmc,sync-write; /* GPMC_CONFIG1_WRITETYPE_ASYNC */
gpmc,clk-activation-ns = <0>; /* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
gpmc,burst-length = <16>; /* GPMC_CONFIG1_PAGE_LEN(2) */
gpmc,mux-add-data = <2>; /* GPMC_CONFIG1_MUXTYPE(2) */

gpmc,sync-clk-ps = <20000>; /* CONFIG2 */

gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <100>;
gpmc,cs-wr-off-ns = <40>;

gpmc,adv-on-ns = <0>; /* CONFIG3 */
gpmc,adv-rd-off-ns = <20>;
gpmc,adv-wr-off-ns = <20>;

gpmc,we-on-ns = <20>; /* CONFIG4 */
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <20>;
gpmc,oe-off-ns = <100>;

gpmc,page-burst-access-ns = <20>; /* CONFIG 5 */
gpmc,access-ns = <80>;
gpmc,rd-cycle-ns = <120>;
gpmc,wr-cycle-ns = <60>;
gpmc,wr-access-ns = <40>; /* CONFIG 6 */
gpmc,wr-data-mux-bus-ns = <20>;

/*gpmc,bus-turnaround-ns = <40>;*/ /* CONFIG6:3:0 = 4 */
gpmc,cycle2cycle-samecsen; /* CONFIG6:7 = 1 */
gpmc,cycle2cycle-delay-ns = <20>; /* CONFIG6:11:8 = 4 */

/* not using dma engine yet, but we can get the channel number here */
dmas = <&edma 1>;
dma-names = "cscdma";

};
};

evm.h file:

Fullscreen U-boot - am335x_evm.txt Download

/*
 * am335x_evm.h
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __CONFIG_AM335X_EVM_H
#define __CONFIG_AM335X_EVM_H

#include <configs/ti_am335x_common.h>
/*uboot debug prints added by astra*/ 
#define DEBUG
#define SF_DEFAULT_BUS 1
/*UBI FS support added by astra*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
/*added by astra*/
#define CONFIG_DRIVER_TI_CPSW
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
#endif
#define CONFIG_SYS_BOOTM_LEN		(16 << 20)

#define CONFIG_MACH_TYPE		MACH_TYPE_AM335XEVM

/* Clock Defines */
#define V_OSCK				25000000  /* Clock output from T2 */
#define V_SCLK				(V_OSCK)

/* Custom script for NOR */
#define CONFIG_SYS_LDSCRIPT		"board/ti/am335x/u-boot.lds"

/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE			(128 << 10)

#ifdef CONFIG_NAND
#define NANDARGS \
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
	"nandrootfstype=ubifs rootwait=1\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
		"nand read ${loadaddr} NAND.kernel; " \
		"bootz ${loadaddr} - ${fdtaddr}\0"
#else
#define NANDARGS ""
#endif

#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
	"bootcmd_" #devtypel #instance "=" \
	"setenv mmcdev " #instance"; "\
	"setenv bootpart " #instance":2 ; "\
	"run mmcboot\0"

#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
	#devtypel #instance " "

#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
	"bootcmd_" #devtypel "=" \
	"run nandboot\0"

#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
	#devtypel #instance " "

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(LEGACY_MMC, legacy_mmc, 0) \
	func(MMC, mmc, 1) \
	func(LEGACY_MMC, legacy_mmc, 1) \
	func(NAND, nand, 0) \
	func(PXE, pxe, na) \
	func(DHCP, dhcp, na)

#include <config_distro_bootcmd.h>

#ifndef CONFIG_SPL_BUILD
#include <environment/ti/dfu.h>
#include <environment/ti/mmc.h>

#define CONFIG_EXTRA_ENV_SETTINGS \
	DEFAULT_LINUX_BOOT_ENV \
	DEFAULT_MMC_TI_ARGS \
	DEFAULT_FIT_TI_ARGS \
	"bootpart=0:2\0" \
	"bootdir=/boot\0" \
	"bootfile=zImage\0" \
	"fdtfile=undefined\0" \
	"console=ttyO0,115200n8\0" \
	"partitions=" \
		"uuid_disk=${uuid_gpt_disk};" \
		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
	"optargs=\0" \
	"ramroot=/dev/ram0 rw\0" \
	"ramrootfstype=ext2\0" \
	"spiroot=/dev/mtdblock4 rw\0" \
	"spirootfstype=jffs2\0" \
	"spisrcaddr=0xe0000\0" \
	"spiimgsize=0x362000\0" \
	"spibusno=0\0" \
	"spiargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"root=${spiroot} " \
		"rootfstype=${spirootfstype}\0" \
	"ramargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"root=${ramroot} " \
		"rootfstype=${ramrootfstype}\0" \
	"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
	"spiboot=echo Booting from spi ...; " \
		"run spiargs; " \
		"sf probe ${spibusno}:0; " \
		"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
		"bootz ${loadaddr}\0" \
	"ramboot=echo Booting from ramdisk ...; " \
		"run ramargs; " \
		"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
	"findfdt="\
		"if test $board_name = A335BONE; then " \
			"setenv fdtfile am335x-bone.dtb; fi; " \
		"if test $board_name = A335BNLT; then " \
			"setenv fdtfile am335x-boneblack.dtb; fi; " \
		"if test $board_name = BBBW; then " \
			"setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \
		"if test $board_name = BBG1; then " \
			"setenv fdtfile am335x-bonegreen.dtb; fi; " \
		"if test $board_name = BBGW; then " \
			"setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \
		"if test $board_name = BBBL; then " \
			"setenv fdtfile am335x-boneblue.dtb; fi; " \
		"if test $board_name = A33515BB; then " \
			"setenv fdtfile am335x-evm.dtb; fi; " \
		"if test $board_name = A335X_SK; then " \
			"setenv fdtfile am335x-evmsk.dtb; fi; " \
		"if test $board_name = A335_ICE && test $ice_mii = rmii; then " \
			"setenv fdtfile am335x-icev2.dtb; fi; " \
		"if test $board_name = A335_ICE && test $ice_mii = mii; then " \
			"setenv fdtfile am335x-icev2-prueth.dtb; fi; " \
		"if test $fdtfile = undefined; then " \
			"echo WARNING: Could not determine device tree to use; fi; \0" \
	"init_console=" \
		"if test $board_name = A335_ICE; then "\
			"setenv console ttyO0,115200n8;" \
		"else " \
			"setenv console ttyO0,115200n8;" \
		"fi;\0" \
	NANDARGS \
	NETARGS \
	DFUARGS \
	BOOTENV
#endif

/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */

#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2

/* PMIC support */
#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910

/* SPL */
#ifndef CONFIG_NOR_BOOT
/* Bootcount using the RTC block */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
#define CONFIG_SYS_BOOTCOUNT_BE

/* USB gadget RNDIS */
#endif

#ifdef CONFIG_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					 CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12, 13, 14, 15, 16, 17, \
					 18, 19, 20, 21, 22, 23, 24, 25, \
					 26, 27, 28, 29, 30, 31, 32, 33, \
					 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 43, 44, 45, 46, 47, 48, 49, \
					 50, 51, 52, 53, 54, 55, 56, 57, }

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	14
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
#endif
#endif /* !CONFIG_NAND */

/*
 * For NOR boot, we must set this to the start of where NOR is mapped
 * in memory.
 */
#ifdef CONFIG_NOR_BOOT
#define CONFIG_SYS_TEXT_BASE		0x08000000
#endif

/*
 * USB configuration.  We enable MUSB support, both for host and for
 * gadget.  We set USB0 as peripheral and USB1 as host, based on the
 * board schematic and physical port wired to each.  Then for host we
 * add mass storage support and for gadget we add both RNDIS ethernet
 * and DFU.
 */
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST

/*
 * Disable MMC DM for SPL build and can be re-enabled after adding
 * DM support in SPL
 */
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
#undef CONFIG_DM_USB
#endif

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* Remove other SPL modes. */
/* disable host part of MUSB in SPL */
/* disable EFI partitions and partition UUID support */
#endif

/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
#define DFUARGS \
	DFU_ALT_INFO_EMMC \
	DFU_ALT_INFO_MMC \
	DFU_ALT_INFO_RAM \
	DFU_ALT_INFO_NAND
#endif

/*
 * Default to using SPI for environment, etc.
 * 0x000000 - 0x020000 : SPL (128KiB)
 * 0x020000 - 0x0A0000 : U-Boot (512KiB)
 * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
 * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
 * 0x0E0000 - 0x442000 : Linux Kernel
 * 0x442000 - 0x800000 : Userland
 */
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000

#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
#elif defined(CONFIG_EMMC_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV		1
#define CONFIG_SYS_MMC_ENV_PART		2
#define CONFIG_ENV_OFFSET		0x0
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_SYS_MMC_MAX_DEVICE	2
#elif defined(CONFIG_NOR_BOOT)
#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
#elif defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_OFFSET		0x001c0000
/*#define CONFIG_ENV_OFFSET_REDUND	0x001e0000*/
#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
#endif

/* SPI flash. */
#define CONFIG_SF_DEFAULT_SPEED                48000000           
#define CONFIG_SF_DEFAULT_MODE                 SPI_MODE_3    
/* Network. */
#define CONFIG_PHY_SMSC
/* Enable Atheros phy driver */
/*added by astra*/
/*#define CONFIG_PHY_ATHEROS*/

/*
 * NOR Size = 16 MiB
 * Number of Sectors/Blocks = 128
 * Sector Size = 128 KiB
 * Word length = 16 bits
 * Default layout:
 * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
 * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
 * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
 * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
 * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
 */
#if defined(CONFIG_NOR)
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_SYS_MAX_FLASH_SECT	128
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BASE		(0x08000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#endif  /* NOR support */

#ifdef CONFIG_DRIVER_TI_CPSW
#define CONFIG_CLOCK_SYNTHESIZER
#define CLK_SYNTHESIZER_I2C_ADDR 0x65
#endif
/*added by astra*/
/* CPSW Ethernet */
#define CONFIG_BOOTP_DNS                /* Configurable parts of CMD_DHCP */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT          10     
#define CONFIG_DRIVER_TI_CPSW           /* Driver for IP block */
#define CONFIG_MII                      /* Required in net/eth.c */


#endif	/* ! __CONFIG_AM335X_EVM_H */

0 Brad Griffis over 6 years ago in reply to Chinmay Pramod

TI__Guru*** 125430 points

What is the full orderable part number of the memory IC (including speed grade)? Is it DDR2 or DDR3? Your current configuration is for DDR2. Does that correspond with what you're ordering? I just made a small update to the DSS script to explicitly output the configured DDR type to make that more obvious.

0 Chinmay Pramod over 6 years ago in reply to Brad Griffis

Intellectual 460 points

Dear Brad,

The part number for the ddr used is MT41K256M16TW-107 XIT:P from micron. The Script is detecting it as DDR2 instead of DDR3.
We have run the same script on an similar working board with the same DDR part number with different trace length and with the same SPL file loaded through uart, where it is detected as DDR3. We have done the DDR s/w leveling and tested it working with the gel file, Both DDR tests passed. But It seems that the SPL is unable to configure the DDR , can you please help in solving this issue.

Regards,
Chinmay

0 Brad Griffis over 6 years ago in reply to Chinmay Pramod

TI__Guru*** 125430 points

Chinmay,

Looks like you have a software issue in u-boot. The configuration being applied to the EMIF is not the right one. None of the registers are correct:

* SDRAM_CONFIG is being configured to operate as DDR2.
* SDRAM_TIM_1/2/3 do not match your spreadsheet.

The TI u-boot code reads the EEPROM do determine the board ID and apply the proper DDR configuration. Have you made appropriate updates so that it's not trying to read the EEPROM? This is a common place for errors.

Brad

0 sandeep motupalli over 6 years ago in reply to Brad Griffis

Prodigy 220 points

Etch length _DDR_net report.xlsxhi Brad,

Sorry for delay in reply, i am attaching the trace lengths of my DDR3 to processor please let us know any errors in the trace lengths

Regards.

Sandeep

0 Kemal R. Shakir over 6 years ago in reply to sandeep motupalli

TI__Guru 55345 points

Hello Sandeep,

Can you also attach the logs from the linked DDR diagnostic scripts in this post?

Best regards,
Kemal

0 Brad Griffis over 6 years ago in reply to Kemal R. Shakir

TI__Guru*** 125430 points

Sandeep,

Let me clarify on the status of this thread:

1. Your attached output from earlier clearly showed that the wrong DDR configuration was being applied by software. This likely points to an issue with improper board identification at run-time.

2. At one point I asked for the trace lengths, but that was before I knew there was a major software configuration issue.

3. I have made significant updates to the ddr-analysis script since you ran it last time, so please download the latest copy before running it:

http://git.ti.com/sitara-dss-files/am335x-dss-files/blobs/raw/master/am335x-ddr-analysis.dss

Please attach the resulting *.txt file (i.e. don't paste the contents).

Thanks,
Brad

0 Brad Griffis over 6 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

PS. I had a look on your trace lengths. The only thing that stood out was the ODT signal which is 156 mils shorter than your CLK. On your next board spin I recommend lengthening that signal to match the rest of the ADDR_CTRL lengths.

Processors

Processors forum

Linux/AM3359: Issue in loading U-boot-SPL