DM368 Bus width on CE0 and CE1

Loris Ciferni

Dear Sirs,

with reference to the DM368 device we need to use the CE0 at 16bit, in order to boot from an external NorFlash (AEMIF Config EM_A[10:8]=101b and BOOT Config EM_A[13:11]=001b), and the CE1 at 8bit because we have an SRAM and a Nand Flash byte oriented. Does is possible to differentiate per chip select the width of the Expansion Bus? Or we have to boot at 8bit from a Nor Flash byte oriented?

Thank you for your cooperation.

Loris

over 14 years ago

0 Tai Nguyen over 14 years ago

TI__Expert 5955 points

Hi Loris,

Yes, it is possible to differentiate per chip select the width of the AEMIF bus. Each CS has its own Asynchronous Configuration register to configure the bus width but in order to boot from external NOR Flash using CE0 in 16 bit mode, you would have to tie the AECFG[2] to a "1". Please refer to the DS (SPRS457D) section 3.7.5.

Thanks,

Tai

0 Loris Ciferni over 14 years ago in reply to Tai Nguyen

Prodigy 70 points

Hi Tai,

thank you for your precious contribution, I've checked your suggestion.

Loris

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DM368 Bus width on CE0 and CE1