TDA3MA: Application stops at "Jumping to IPU1 CPU0 App"

Hi Rishabh,

Thank you so much. Yes, they are using OCMC RAM. They moved the code to DDR and didn't see the issue. Can you please explain the reason and how to use OCMC RAM with SD boot?

Best regards,

Ken

Hi Rishabh,

Yes, they are using all CPUs. Does it mean only data section can be used after IPU1 C0 starts? They were using OCMC RAM for code section.

Best regards,
Ken

Hi Rishabh,

We are trying to split OCMC_RAM into two sections
from
OCMC_RAM 40300000 00080000 00000000 00080000 RWIX
to
OCMC_RAM0 40300000 00000400 00000000 00000400 RWIX
OCMC_RAM1 40300400 0007fc00 00000000 0007fc00 RWIX

and place the code to OCMC_RAM1. We changed mem_segment_definition_512mb.xs and confirmed EVE memory map changed correctly. For DSP memory map, however, nothing changed. Can you kindly let us know how to change DSP internal memory section as above?

Best regards,
Ken

Hi Rishabh,

As you suggested, I want to keep first 1 KB of OCMC as reserved (OCMC_RAM0) and use the later 511 KB portion as OCMC_RAM1. I want to know how to do this.

Best regards,
Ken

Hi Rishabh,

Let me know the file name and where it is.

Best regards,
Ken

Hi Ken,

The file is PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\build\tda3xx\mem_segment_definition_512mb.xs.

Regards,
Rishabh

Hi Rishabh,

Please let me know the file name and where it is.

Best regards,
Ken

Hi Rishabh,

Please ignore my previous comment.

As I said, "mem_segment_definition_512mb.xs" changes memory map for EVE. However it doesn't change memory map for DSP and IPU. Is it the only file we should change?

Best regards,
Ken

Hi Ken,

Yes this is the only file you need to change. EVE uses OCMC RAM, DSP and IPU don't.
Hence you see changes only in EVE.

Also TIDL(running on DSP) uses OCMC but that address is hard coded.
TIDL will not start before IPC attach happens, which means boot would have been over.
Then there should not be any abort on IPU_C1.

Regards,
Rishabh

Hi Rishabh,

Here is snippet from the EVE memory map with xs file modifications:

        name            origin    length      used     unused   attr    fill

----------------------  --------  ---------  --------  --------  ----  --------

 OCMC_RAM0             40300000   00000400  00000000  00000400  RWIX

 OCMC_RAM1             40300400   0007fc00  00000000  0007fc00  RWIX

 DSP1_L2_SRAM          40800000   00048000  00000000  00048000  RWIX

 DSP2_L2_SRAM          41000000   00048000  00000000  00048000  RWIX

Here is snippet from the DSP memory map with xs file modifications:

        name            origin    length      used     unused   attr    fill

----------------------  --------  ---------  --------  --------  ----  --------

 L2SRAM                00800000   00038000  00038000  00000000  RW X

 OCMC_RAM              40300000   00080000  00000600  0007fa00  RWIX

 DSP1_L2_SRAM          40800000   00048000  00000000  00048000  RWIX

As you can see, OCMC_RAM is not split into two parts (OCMC_RAM0 and OCMC_RAM1) in DSP side. My xs file is attached. Did I miss something?

mem_segment_definition_512mb.zip

Best regards,

Ken  

Hi Rishabh,

Yes, i did clean build but the result was same.

In the original xs file, there is following code:
if( core == "arp32_1" )
{
memory[index++] = ["OCMC_RAM1", {
comment: "OCMC_RAM1",
name: "OCMC_RAM1",
base: OCMC1_ADDR,
len: OCMC1_SIZE
}];
}

From this, OCMC_RAM1 is created only for EVE. If we look DSP and IPU memory map file, the section name is "OCMC_RAM" (not "OCMC_RAM1"). Is DSP and IPU memory section, especially OCMC, created from xs file? I'm wondering if there is another file to set (create) memory section for OCMC for DSP and IPU.

Best regards,
Ken

Hi Rishabh,

Thank you. We will try this next week and get back to you.

Best regards,

Ken