Part Number: AM6548
Hi,
We are designing a board with AM6548 and LPDDR4 Micron part MT53E128M32D2DS-053 AIT:A.
We are referring to Board Design and Layout_spraci2 guidelines document provided by TI.
According to the document, we have length matched the signals as follows:
1. ADDR_CTRL_A with CK0
2. ADDR_CTRL_B With CK1
3. Byte 0 with DQS0, Byte 1 with DQS1, Byte 2 with DQS2, Byte 3 with DQS3
4. Length matched between CK0 and CK1 - 3ps
Please clarify on the following points:
1. Do we have to consider Package length while length matching. If yes, could you provide us this information.
2. Do we have to length match DQS with clock signals
3. Please confirm if any additional length match constraints are to be followed
Please revert back at your earliest convenience.
Thanks and Regards,
Sushruta
