RTOS/TDA2PXEVM: issCaptDrvCallback() is never called.

Hi Frank,

What is the software you are using to test this?

Thanks and Regards,
Piyali

Hi Piyali,

    I use Vision SDK and Tera Term.

Best,

Frank

Thanks Frank!
Could you please help us understand which version of the SDK you are using and what is the usecase you are running?

To check for the timing match between Lattice and TDA2px, could you also please check if there is any peculiarity with the Lattice CSI timing requirements?

Regards,
Piyali

Hi Piyali,

      I am using the PROCESSOR_SDK_VISION_03_06_00_00 and radar_capture_only usecase. I don't think there is any peculiarity for the Lattice CSI timing requirement. Enclosed please find the timing parameters for CSI2 Tx IP from Lattice.

Thanks,

Frank

Hi Frank,

Can you please check on the following

• Can you please ensure the CSI2 clock rates are configured correctly on TDA2Px side. i.e. While creating the driver we will have to specify the CSI2 clock rate, it take in DDR format (for 800 Mbps data rate, clock should be specified as 400 Mhz)
• Can you please start FPGA to stream after TDA2Px CSI2 driver has been created and waiting to receive data

Regards, Sujith

Hi Sujith,

     Thank you for your reply. The CSI2 clock rate is correct. For the CSI2 driver, do you mean the IssCapture? 

     Since I only use the TDA2px evaluation board and our own custom FPGA board, is there any board information should I modify? I think I set the boardID to BSP_BOARD_BASE_TDA2PX and Bsp_BoardRev to BSP_BOARD_REV_A, is it correct? 

     Is there any way that I can verify the status of IssCapture? Do you have any recommend usecase? I want to make sure my code and setup are correct. There is no error during the compilation and running. If you need, I can provide the source code.

Best,

Frank

    

Hi Frank,

Yes, when i say CSI2 driver, i mean issCapture.

If the clock is configured correctly, please check on the connection. I am not sure how the FPGA is connected to CSI2 receiver pins. Could you please cross check on the connection (ensure +/- combinations are ok, even if they are swapped, we can configure while creating the driver. )

Important to start the issCapture driver first and then start the FPGA (to rule out, source not waiting for termination to be enabled)

Also, check at 0x42213304, if 29th bit is set, it would indicate LP transitions have been successful.

Regards, Sujith