RTOS/TDA2SX: TDA2 A15 generic timer

Yang Wang

Prodigy 190 points

Part Number: TDA2SX
Other Parts Discussed in Thread: TDA2

Tool/software: TI-RTOS

Hi,

I try to use generic timer as MPU system tick source, but I found that only IPU 1_0 boots normally.

What should I do to use generic timer?

Thanks&Regards.

over 6 years ago

0 Yordan Kamenov over 6 years ago

TI__Mastermind 42515 points

Hi,

can you check chapter "7.1.2 BIOS Tick and Time Stamp Provider Concerns" in vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_DevelopmentGuide.pdf and see if it can give you some directions?

Regards,
Yordan

0 Rishabh Garg over 6 years ago

TI__Guru 55685 points

Hi Yang,

Can you explain what you mean by "only IPU 1_0 boots normally".
Also MPU timer is used by TDA2 SBL. You can refer to the same.

Regards,
Rishabh

0 Yang Wang over 6 years ago in reply to Rishabh Garg

Prodigy 190 points

Hi,
On the UART console, I can only find logs output by IPU 1_0.

0 Rishabh Garg over 6 years ago in reply to Yang Wang

TI__Guru 55685 points

Hi Yang,

Can you share the UART log?

Regards,
Rishabh

0 Yang Wang over 6 years ago in reply to Rishabh Garg

Prodigy 190 points

Hi,
I have found the reason. When A15 idle and execute PMLIBCpuIdle function, A15 sleeps and its clock is gated. This results in generic timer stopping work, so A15 can not be waked up by system tick.

0 Yang Wang over 6 years ago in reply to Rishabh Garg

Prodigy 190 points

I have another question. In function PmlibDoWFI, ACTLR.SMP is set to 0. But I can't find this bit is enabled again after wake-up.
When SMP bit is set again?

0 Piyali Goswami over 6 years ago in reply to Yang Wang

TI__Mastermind 30245 points

Hi Yang,

Yes.. the timer inside the A15 would stop if clock gated. You should used the SoC level GP Timers for the OS Tick instead to allow the A15 to wake up from low power.

Thanks and Regards,
Piyali

0 Piyali Goswami over 6 years ago in reply to Yang Wang

TI__Mastermind 30245 points

Yang,

The SMP bit should be set again in the ISR context which after it wakes up. Are you using the dual A15 subsystem in SMP mode? If no, then you would not need to set this back to 1. However, if you are setting the A15 to work in SMP mode you would need to set the ACTLR.SMP in the ISR routine which is run after the A15 wakes up from low power.

Thanks and Regards,
Piyali

0 Yang Wang over 6 years ago in reply to Piyali Goswami

Prodigy 190 points

Hi, Piyali

Yes, I am using MPU in SMP mode.
OK. So user should be responsible for setting SMP bit again. I think this is not convenient, because every ISR should do this in theory.
Is it necessary that disable SMP before sleep?
Is the reason for clearing SMP bit that A15 power is placed in retention state after sleep?

0 Piyali Goswami over 6 years ago in reply to Yang Wang

TI__Mastermind 30245 points

Hi Yang,

The clearing of ACTLR.SMP bit is required before going to retention or placing the Cortex A15 in power off mode (power down modes).
You need not to place the setting of SMP in all user ISR routines. This is only required in the function which is called when IRQ or FIQ is triggered. (2 interrupts). The other user-defined ISRs are called only after this from these two functions.
You can skip this if you are only getting the A15s to clock gated (power on) state.

Thanks and Regards,
Piyali

0 Yang Wang over 6 years ago in reply to Piyali Goswami

Prodigy 190 points

Hi Piyali,

OK. Thank you!
By the way, I think TI should update SDK or at least make a statement about this.

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RTOS/TDA2SX: TDA2 A15 generic timer