Linux/TDA2EXEVM: Cache_wb how to use

shuai wang32

Genius 4770 points

Part Number: TDA2EXEVM

Tool/software: Linux

i use EDMA_UTILS_memcpy2D in c66 dsp to copy data from DDR to L2 ,

but sometimes Inconsistency between target data and source data ，

so Cache_wb source data befer EDMA_UTILS_memcpy2D ,

but when i run the program it crash ,follow is the log

368990] omap_l3_noc 44000000.ocp: L3 application error: target 5 mod:1 (unclearable)
[ 36.499785] omap_l3_noc 44000000.ocp: L3 debug error: target 5 mod:1 (unclearable)
THANKS

Shuai

over 6 years ago

0 Brijesh Jadav over 6 years ago

TI__Guru**** 481095 points

Hi Shui,

Please call Cache_wb after memcpy. Please note that if you are doing DMA copy, they you dont need to call cache-wb. Bu also if you try to access on DSP copied buffer, pls do cache_inv before accessing updated buffer.

Rgds,
Brijesh

0 shuai wang32 over 6 years ago in reply to Brijesh Jadav

Genius 4770 points

Hi Brijesh
src is on DDR dst is on L2
after EDMA_UTILS_memcpy2D((void*)(dst), (const void *)src , width * sizeof(short), height, blkWidth * sizeof(short), width * sizeof(short));
i compear dst and src is not the same ,
you mean i have to cache_inv(dst, width * sizeof(short)*height, 1); after EDMA_UTILS_memcpy2D ?
Thanks
Shuai

0 Brijesh Jadav over 6 years ago in reply to shuai wang32

TI__Guru**** 481095 points

Hi Shuai,

It is simple, if you are trying to access this shared buffer via CPU, you need to do cach_inv before accessing it and if you update this shared buffer, then after updating, do cache_wb..

Regards,
Brijesh

0 shuai wang32 over 6 years ago in reply to Brijesh Jadav

Genius 4770 points

Hi :Brijesh
but if i use Cache_wb , it have some crash.
368990] omap_l3_noc 44000000.ocp: L3 application error: target 5 mod:1 (unclearable)
[ 36.499785] omap_l3_noc 44000000.ocp: L3 debug error: target 5 mod:1 (unclearable)
thanks
Shuai

0 Brijesh Jadav over 6 years ago in reply to shuai wang32

TI__Guru**** 481095 points

Hi Shuai,

I guess you are doing EDMA copy from memory to L2 and from which memory you do cache_wb? Are you making internal memory(L2) cached? If it is not, cache_wb may not be required for reading L2 memory..

Rgds,

Brijesh

Processors

Processors forum

Linux/TDA2EXEVM: Cache_wb how to use